Method for building up a fan-out RDL structure with fine pitch line-width and line-spacing

1. A method of making a semiconductor device, comprising:

providing a plurality of semiconductor die as a semiconductor wafer;

forming a third insulating layer over an active surface of the semiconductor wafer;

forming a third opening in the third insulating layer, wherein the third opening is elongated in a first direction parallel to the active surface of the semiconductor wafer such that a length of the third opening is greater than a width of the third opening and the length and width of the third opening are both parallel to the active surface of the semiconductor wafer;

forming a fourth insulating layer over the semiconductor wafer and third insulating layer;

forming a fourth opening in the fourth insulating layer aligned with the third opening in the third insulating layer, wherein the fourth opening is elongated in a second direction substantially perpendicular to the first direction and parallel to both the width of the third opening and the active surface such that the fourth opening extends outside a footprint of the third opening and the third opening extends outside a footprint of the fourth opening;

singulating the plurality of semiconductor die from the semiconductor wafer after forming the third insulating layer, third opening, fourth insulating layer, and fourth opening;

disposing the plurality of semiconductor die on a carrier with the third insulating layer and fourth insulating layer oriented toward the carrier;

depositing an encapsulant over the carrier and plurality of semiconductor die to cover a back surface of the plurality of semiconductor die opposite the active surface, wherein a first surface of the encapsulant is coplanar with a surface of the fourth insulating layer opposite the semiconductor die;

forming a backside insulating layer over a second surface of the encapsulant opposite the first surface of the encapsulant while the semiconductor die and encapsulant remain on the carrier, wherein the backside insulating layer includes a higher resistance to wear than the encapsulant and a portion of the encapsulant extends between the backside insulating layer and the back surface of the plurality of semiconductor die;

removing the carrier after forming the backside insulating layer;

forming a first insulating layer over the first surface of the encapsulant and the active surface of the plurality of semiconductor die after forming the backside insulating layer, wherein the first insulating layer extends into the third opening of the third insulating layer and the fourth opening of the fourth insulating layer;

forming a first opening in the first insulating layer aligned with the third opening of the third insulating layer and the fourth opening of the fourth insulating layer, wherein a footprint of the first opening is completely within the footprint of the third opening and the footprint of the fourth opening;

forming a conductive layer over the first insulating layer and extending into the first opening in the first insulating layer to contact the semiconductor die, wherein the first insulating layer creates a physical separation between the conductive layer and the third insulating layer; and

singulating through the encapsulant and backside insulating layer, thereby separating each of the plurality of semiconductor die into individual packages.

2. The method of claim 1 , further including forming the conductive layer to include a line-pitch or line-spacing of less than 5 μm.

3. The method of claim 1 , further including:

disposing an interconnect component adjacent to one of the plurality of semiconductor die; and

depositing the encapsulant over the plurality of semiconductor die and interconnect component.

4. The method of claim 1 , further including:

forming a trench in the first insulating layer;

forming the conductive layer in the trench; and

planarizing the first insulating layer and conductive layer using a grinding or polishing operation.

5. The method of claim 1 , further including:

disposing a 3D interconnect unit on the carrier; and

depositing the encapsulant over the semiconductor die and 3D interconnect unit.

6. The method of claim 1 , further including forming the conductive layer to include a contact pad directly over the first opening, third opening, and fourth opening, wherein the contact pad is elongated in the first direction.

7. The method of claim 1 , wherein a portion of the third insulating layer is exposed in the fourth opening and a portion of the fourth insulating layer contacts a contact pad of the semiconductor wafer within the third opening.

8. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a first insulating layer over an active surface of the semiconductor die including a first opening through the first insulating layer elongated in a first direction parallel to the active surface of the semiconductor die;

forming a second insulating layer over the active surface of the semiconductor die including a second opening through the second insulating layer elongated in a second direction, wherein the second direction is substantially perpendicular to the first direction and parallel to the active surface of the semiconductor die;

disposing the semiconductor die on a carrier with the first insulating layer and second insulating layer oriented toward the carrier;

depositing an encapsulant over the semiconductor die and carrier with a back surface of the encapsulant extending over a back surface of the semiconductor die;

forming a backside insulating layer over the back surface of the encapsulant while the semiconductor die and encapsulant remain on the carrier, wherein the backside insulating layer includes a greater resistance to wear than the encapsulant;

forming a third insulating layer over the encapsulant, first insulating layer, and second insulating layer, wherein the third insulating layer extends into the first opening and second opening;

forming a third opening in the third insulating layer, wherein a footprint of the third opening is completely within a footprint of the first opening and a footprint of the second opening; and

forming a conductive layer over the third insulating layer and into the third opening of the third insulating layer after depositing the encapsulant.

9. The method of claim 8 , further including:

disposing an interconnect component adjacent to the semiconductor die; and

depositing the encapsulant over the semiconductor die and interconnect component.

10. The method of claim 8 , further including forming the conductive layer to include a line-pitch or line-spacing of less than 5 μm.

11. The method of claim 8 , wherein the active surface of the semiconductor die is recessed within the encapsulant.

12. The method of claim 8 , further including forming the backside insulating layer prior to forming the conductive layer.

13. The method of claim 8 , further including:

forming a trench in the third insulating layer;

forming the conductive layer in the trench; and

planarizing the third insulating layer and conductive layer.

14. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a first insulating layer over an active surface of the semiconductor die including a first opening through the first insulating layer;

forming a second insulating layer over the active surface of the semiconductor die including a second opening through the second insulating layer extending into the first opening, wherein a first portion of a perimeter of the second opening is within a footprint of the first opening and a second portion of the perimeter of the second opening is outside a footprint of the first opening;

disposing the semiconductor die on a carrier;

depositing an encapsulant over the semiconductor die and carrier with an active surface of the semiconductor die recessed in the encapsulant, a first surface of the encapsulant extending over a back surface of the semiconductor die, and a second surface of the encapsulant that is coplanar with the second insulating layer;

depositing a backside insulating layer onto the encapsulant to cover substantially all of the first surface of the encapsulant while the semiconductor die remains on the carrier;

forming a third insulating layer over the second surface of the encapsulant opposite the first surface of the encapsulant while the backside insulating layer remains covering substantially all of the first surface of the encapsulant; and

forming a third opening through the third insulating layer, wherein a footprint of the third opening is completely within a footprint of the first opening.

15. The method of claim 14 , further including forming a conductive layer over the semiconductor die.

16. The method of claim 15 , further including forming the backside insulating layer and third insulating layer prior to forming the conductive layer.

17. The method of claim 15 , further including forming the conductive layer to include a line-pitch or line-spacing of less than 5 μm.

18. The method of claim 15 , further including forming the conductive layer in the third opening without the conductive layer contacting the first insulating layer.

19. The method of claim 14 , further including forming the first opening, second opening, and third opening directly over a contact pad on the semiconductor die.

20. The method of claim 14 , wherein the backside insulating layer includes a resistance to wear greater than a resistance to wear of the encapsulant.

21. The method of claim 19 , wherein the third opening exposes the contact pad without exposing the first insulating layer and without exposing the second insulating layer.

22. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a first insulating layer over an active surface of the semiconductor die including a first opening through the first insulating layer;

forming a second insulating layer over the active surface of the semiconductor die including a second opening through the second insulating layer, wherein a first portion of a perimeter of the second opening is within a footprint of the first opening and a second portion of the perimeter of the second opening is outside a footprint of the first opening;

disposing the semiconductor die on a carrier with the first insulating layer and second insulating layer oriented toward the carrier;

depositing an encapsulant over a first surface of the semiconductor die opposite the active surface with a first surface of the encapsulant over and parallel to the first surface of the semiconductor die, wherein the semiconductor die remains on the carrier while depositing the encapsulant; and

depositing a backside insulating layer onto the encapsulant and covering substantially an entirety of the first surface of the encapsulant while the semiconductor die and encapsulant remain on the carrier.

23. The method of claim 22 , further including:

disposing an interconnect component adjacent to the semiconductor die; and

depositing the encapsulant over the semiconductor die and interconnect component.

24. The method of claim 22 , further including forming an interconnect structure over the active surface of the semiconductor die while the backside insulating layer remains covering substantially the entirety of the first surface of the encapsulant.

25. The method of claim 24 , further including:

forming the second insulating layer prior to depositing the encapsulant;

forming the second opening after depositing the first insulating layer; and

forming the interconnect structure extending into the second opening.