Insulating layer for planarization and definition of the active region of a nanowire device

1. A method of fabricating a semiconductor device, comprising:

forming a plurality of nanowires on a support, wherein each nanowire comprises a first conductivity type semiconductor core and a second conductivity type semiconductor shell over the core;

forming an insulating material layer over at least a portion of the plurality of nanowires such that at least a portion of the insulating material layer provides a substantially planar top surface;

removing a portion of the insulating material layer to define an active region of nanowires;

forming an electrical contact over the substantially planar top surface of the insulating material layer; and

forming a conductive material layer over at least a portion of the insulating material layer and the plurality of nanowires in the active region,

wherein the electrical contact is electrically connected to the conductive material layer; and

wherein the conductive material layer contacts the nanowires in the active region and contacts the insulating material layer over the substantially planar top surface, wherein the electrical contact is formed on the conductive material.

2. The method of claim 1 , wherein the device comprises a nanowire LED.

3. The method of claim 2 , wherein the first conductivity type semiconductor core and the second conductivity type semiconductor shell are configured to form a pn or pin junction that in operation provides an active region for light generation.

4. The method of claim 1 , wherein forming the insulating material comprises depositing the insulating material using a low temperature oxide (LTO) deposition process.

5. The method of claim 4 , wherein the insulating material is deposited at a temperature less than about 750° C.

6. The method of claim 4 , wherein the insulating material is deposited by chemical vapor deposition (CVD).

7. The method of claim 4 , wherein the insulating material comprises Al 2 O 3 or SiO 2 .

8. The method of claim 1 , wherein removing a portion of the insulating material layer comprises etching the insulating material layer through a mask.

9. The method of claim 8 , wherein the etching removes the insulating material layer from the active region without etching the nanowires.

10. The method of claim 8 , wherein the insulating material is wet etched.

11. The method of claim 10 , wherein the insulating material is wet etched using a hydrofluoric acid solution.

12. The method of claim 1 , further comprising maintaining a portion of the insulating material to provide a boundary around the active region of nanowires.

13. The method of claim 1 , wherein removing a portion of the insulating material layer comprises etching the insulating material layer through a first mask to define the active region of nanowires, the method further comprising:

etching through a second mask to remove nanowires and a portion of the conductive material layer to expose a portion of the support;

forming a third mask over the device having a first opening over the conductive material layer and over the planar top surface of the insulating material layer and a second opening over the exposed portion of the support;

depositing a metal material within the first opening to form the electrical contact electrically connected to the conductive material layer;

depositing a metal material within the second opening to form the second electrical contact over the exposed portion of the support; and

removing the third mask.

14. The method of claim 13 , further comprising:

forming a passivation layer over the active region of the device.

15. The method of claim 14 , wherein the passivation material comprises photosensitive epoxy.

16. The method of claim 13 , wherein the metal material comprises one or more of aluminum, titanium and gold.

17. The method of claim 1 , further comprising:

removing a first plurality of nanowires outside of the active region to provide a first substantially flat portion prior to forming the insulating material layer, wherein the substantially planar top surface of the insulating material layer is located over the first substantially flat portion.

18. The method of claim 17 , further comprising:

removing a second plurality of nanowires outside the active region to provide a second substantially flat portion, wherein the second electrical contact is formed in the second substantially flat portion.

19. The method of claim 18 , wherein removing the first plurality of nanowires and the second plurality of nanowires to provide the respective first and second substantially flat portions comprises etching the nanowires through a first mask, and wherein removing a portion of the insulating material layer comprises etching the insulating material layer through a second mask to define the active region of nanowires, the method further comprising:

etching the conductive material layer and the insulating material layer through a third mask to provide the exposed portion of the support;

forming a fourth mask over the device having a first opening over the planar top surface of the insulating material layer and a second opening over the exposed portion of the support;

depositing a metal material within the first opening to form the electrical contact electrically connected to the conductive material layer;

depositing a metal material within the second opening to form the second electrical contact over the exposed portion of the support; and

removing the fourth mask.

20. The method of claim 19 , further comprising:

forming a passivation layer over the active region of the device.

21. The method of claim 20 , wherein the passivation material comprises an epoxy-based photoresist.

22. The method of claim 19 , wherein the metal material comprises one or more of aluminum, titanium and gold.

23. A method of fabricating a semiconductor device, comprising:

forming a plurality of nanowires on a support, wherein each nanowire comprises a first conductivity type semiconductor core and a second conductivity type semiconductor shell over the core;

forming an insulating material layer over at least a portion of the plurality of nanowires such that at least a portion of the insulating material layer provides a substantially planar top surface;

removing a portion of the insulating material layer to define an active region of nanowires;

forming an electrical contact over the substantially planar top surface of the insulating material layer;

forming a conductive material layer over at least a portion of the insulating material layer and the plurality of nanowires in the active region, wherein the electrical contact is electrically connected to the conductive material layer;

removing nanowires and a portion of the conductive material layer to expose a portion of the support; and

forming a second electrical contact over the exposed portion of the support.

24. A method of fabricating a semiconductor device, comprising:

forming a plurality of nanowires on a support, wherein each nanowire comprises a first conductivity type semiconductor core and a second conductivity type semiconductor shell over the core;

forming an insulating material layer over at least a portion of the plurality of nanowires such that at least a portion of the insulating material layer provides a substantially planar top surface;

removing a portion of the insulating material layer to define an active region of nanowires;

forming an electrical contact over the substantially planar top surface of the insulating material layer; and

forming a conductive material layer over at least a portion of the insulating material layer and the plurality of nanowires in the active region,

wherein the electrical contact is electrically connected to the conductive material layer;

wherein the device comprises a nanowire LED; and

wherein the conductive material layer comprises a transparent conductive oxide (TCO).

25. The method of claim 24 , wherein the TCO comprises indium tin oxide (ITO).