Semiconductor memory device with a 3-dimensional stacked memory cell structure
View Patent ↗A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
1. A semiconductor memory device, comprising:
a semiconductor substrate;
memory units including memory cells that are stacked above the semiconductor substrate, the memory units including a first memory unit and a second memory unit, the second memory unit being adjacent to the first memory unit in a first direction; and
bit lines disposed above the memory units, the bit lines extending in a second direction across the first direction, the bit lines including a first bit line and a second bit line, the second bit line being adjacent to the first bit line in the first direction, wherein
a first pitch is larger than a second pitch, the first pitch being a pitch between the first memory unit and the second memory unit, the second pitch being a pitch between the first bit line and the second bit line.
2. The semiconductor memory device according to claim 1 , wherein
the bit lines include more than n bit lines and are disposed such that the second pitch is 1/n times the first pitch (n being a natural number),
n bit lines are allocated to one column group of the memory units, and
the n bit lines are electrically connected to n memory units.
3. The semiconductor memory device according to claim 1 , wherein one of the memory units comprises:
a semiconductor body extending in a direction perpendicular to the semiconductor substrate;
a charge storage layer surrounding the semiconductor body; and
word lines surrounding the charge storage layer.
4. The semiconductor memory device according to claim 2 , wherein
a read or write operation is performed to the memory cells in the n memory units electrically connected to the n bit lines simultaneously.
5. The semiconductor memory device according to claim 3 , wherein
a width of the bit line in the first direction is smaller than a width of the semiconductor body in the first direction, and
the semiconductor body and the bit line are connected via a first bit line contact, the first bit line contact having a width smaller than a width of the semiconductor body in the first direction.
6. The semiconductor memory device according to claim 2 , further comprising:
a sense amplifier connected selectively or simultaneously to the n bit lines.
7. The semiconductor memory device according to claim 6 , wherein
a differential type sense amplifier is used as the sense amplifier.
8. The semiconductor memory device according to claim 6 , wherein
the sense amplifier is connected electrically to the first bit line among the n bit lines in which a read or write operation is performed, and the second bit line among the n bit lines other than the first bit line in which the read or write operation is performed is employed as a shield line.
9. The semiconductor memory device according to claim 1 , wherein
the memory units are electrically connected to the bit line.
10. A semiconductor memory device, comprising:
a semiconductor substrate;
memory units including memory cells that are stacked above the semiconductor substrate, the memory units including a first memory unit, a second memory unit, and a third memory unit, the second memory unit being adjacent to the first memory unit along a first line, the third memory unit being adjacent to the first memory unit along a second line across the first line;
bit lines disposed above the memory units, the bit lines extending in a second direction, the bit lines including a first bit line, a second bit line, a third bit line, and a fourth bit line, the first bit line being electrically connected to the first memory unit, the second bit line being electrically connected to the second memory unit, the third bit line being electrically connected to the third memory unit and disposed between the first bit line and the second bit line, the fourth bit line being disposed between the third bit line and the second bit line.
11. The semiconductor memory device according to claim 10 , wherein
a first pitch is larger than a second pitch, the first pitch being a pitch between the first memory unit and the second memory unit, the second pitch being a pitch between the first bit line and the third bit line.
12. The semiconductor memory device according to claim 10 , wherein one of the memory units comprises:
a semiconductor body extending in a direction across the semiconductor substrate;
a charge storage layer surrounding the semiconductor body; and
word lines surrounding the charge storage layer.
13. The semiconductor memory device according to claim 10 , wherein
the memory units further include a fourth memory unit, the fourth memory unit being adjacent to the third memory unit along a third line parallel to the first line,
the bit lines further include a fifth bit line, the fifth bit line being electrically connected to the fourth memory unit.
14. The semiconductor memory device according to claim 13 , wherein
the fifth bit line is located adjacent to the second bit line on an opposite side of the second bit line with respect to the fourth bit line.
15. The semiconductor memory device according to claim 11 , wherein
the bit lines include more than n bit lines and are disposed such that the second pitch is 1/n times the first pitch (n being a natural number),
n bit lines are allocated to one column group of the memory units, and
the n bit lines are electrically connected to n memory units.
16. The semiconductor memory device according to claim 15 , wherein
a read or write operation is performed to the memory cells in the n memory units electrically connected to the n bit lines simultaneously.
17. The semiconductor memory device according to claim 15 , further comprising:
a sense amplifier connected selectively or simultaneously to the n bit lines.
18. The semiconductor memory device according to claim 17 , wherein
a differential type sense amplifier is used as the sense amplifier.
19. The semiconductor memory device according to claim 17 , wherein
the sense amplifier is connected electrically to the first bit line among the n bit lines in which a read or write operation is performed, and the second bit line among the n bit lines other than the first bit line in which the read or write operation is performed is employed as a shield line.
20. The semiconductor memory device according to claim 10 , wherein
the memory units are electrically connected to the bit line.