METHOD FOR PRODUCING TRENCH HIGH ELECTRON MOBILITY DEVICES

1 . A method for producing a solid state device, comprising:

a) on a Silicon substrate having a substantially flat topside and a substantially flat, oppositely disposed bottomside, forming a first dielectric layer over an epitaxial layer at least partially covering the topside;

b) depositing a photoresist material over the first dielectric layer;

c) removing a predetermined portion of the photoresist material to define a negative photoresist pattern;

d) removing a predetermined portion of the first dielectric layer corresponding to the negative photoresist pattern to define an exposed portion;

e) implanting dopants into the exposed portion to define a doped portion;

f) preferentially removing Silicon from the exposed portion to generate trenches having V-shaped cross-sections and having first and second angled sidewalls defining the V-shaped cross-section, wherein each angled sidewall defining the V-shaped cross-section is a Silicon face having a 111 orientation;

g) removing remaining first dielectric layer; and

h) forming a 2DEG on at least one sidewall.

2 . The method of claim 1 and further comprising:

i) depositing a second dielectric layer over the at least one sidewall;

j) forming a first buffer layer at least partially covering the bottomside; and

k) forming at least one ohmic contact in the first buffer layer to define a Drain.

3 . The method of claim 1 and further comprising:

l) depositing a third dielectric layer to fill in trenches and planarize the Silicon substrate.

4 . The method of claim 1 and further comprising:

m) doping the first buffer layer to define a highly doped buffer layer;

n) applying Gate oxides to predetermined portions of the topside to define Gate regions;

o) applying a first metallization layer over predetermined portions of the topside to define Source regions;

p) applying a passivation layer over the first metallization layer;

q) thinning the wafer;

r) activating the respective dopants;

s) applying a second metallization layer over the bottomside; and

t) after s), annealing the wafer;

wherein the passivation layer is between about 1 micron and about 2 microns thick.

5 . The method of claim 1 , wherein step h) further comprises:

h1) applying a growth promoter to the at least one sidewall;

h2) after h1), applying a stress buffer layer to the at least one sidewall;

h3) after h2), forming a first GaN layer on the at least one sidewall;

h4) after h3), forming an Al 27%-GaN layer over the first GaN layer; and

h5) after h4), forming a second GaN layer over the Al 27%-GaN layer.

6 . The method of claim 4 wherein the doped layer has a dopant concentration of between about 10 13 dopants per cubic centimeter and about 10 18 dopants per cubic centimeter; and wherein the highly doped buffer layer has a dopant concentration of between about 10 18 dopants per cubic centimeter and about 10 20 dopants per cubic centimeter.

7 . The method of claim 1 wherein the highly doped buffer layer is between about 1 micron thick and about 3 microns thick; wherein the topside passivation layer is between about 0.4 micron thick and about 0.8 microns thick; and wherein the first dielectric layer is between about 1 Angstrom unit thick and about 10 microns thick.

8 . The method of claim 1 wherein the first dielectric material is selected from the group including SiO 2 , Si 3 N 4 , and combinations thereof.

9 . A method for producing a transistor device, comprising:

a) on a Silicon substrate having a substantially flat topside and a substantially flat, oppositely disposed bottomside, forming a first dielectric layer over an epitaxial layer at least partially covering the topside;

b) depositing a photoresist material over the first dielectric layer;

c) removing a predetermined portion of the photoresist material to define a negative photoresist pattern;

d) removing a predetermined portion of the first dielectric layer corresponding to the negative photoresist pattern to define an exposed portion;

e) implanting dopants into the exposed portion to define a doped portion;

f) preferentially removing Silicon from the exposed portion to generate trenches having V-shaped cross-sections and having first and second angled sidewalls defining the V-shaped cross-section, wherein each angled sidewall defining the V-shaped cross-section is a Silicon face having a 111 orientation;

g) removing remaining first dielectric layer;

h1) applying a growth promoter to the at least one sidewall;

h2) after h1), applying a stress buffer layer to the at least one sidewall;

h3) after h2), forming a first GaN layer on the at least one sidewall;

h4) after h3), forming an Al 27%-GaN layer over the first GaN layer;

h5) after h4), forming a second GaN layer over the Al 27%-GaN layer to yield a 2DEG layer;

i) depositing a second dielectric layer over the at least one sidewall;

j) forming a first buffer layer at least partially covering the bottomside;

k) forming at least one ohmic contact in the first buffer layer to define a Drain;

l) depositing a second dielectric layer to fill in trenches and planarize the Silicon substrate;

m) doping the first buffer layer to define a highly doped buffer layer;

n) applying Gate oxides to predetermined portions of the topside to define Gate regions;

o) applying a first metallization layer over predetermined portions of the topside to define Source regions;

p) applying a passivation layer over the first metallization layer;

q) thinning the wafer;

r) activating the respective dopants;

s) applying a second metallization layer over the bottomside; and

t) after s), annealing the wafer;

wherein the doped layer has a dopant concentration of between about 10 13 dopants per cubic centimeter and about 10 18 dopants per cubic centimeter;

wherein the highly doped buffer layer has a dopant concentration of between about 10 18 dopants per cubic centimeter and about 10 20 dopants per cubic centimeter;

wherein the highly doped buffer layer is between about 1 micron thick and about 3 microns thick;

wherein the topside passivation layer is between about 0.4 micron thick and about 0.8 microns thick;

wherein the first dielectric layer is between about 1 Angstrom unit thick and about 10 microns thick; and

wherein the first dielectric material is selected from the group including SiO 2 , Si 3 N 4 , and combinations thereof.

10 . A method for producing a 2DEG trench transistor device, comprising:

a) providing a Silicon substrate having a substantially flat topside and a substantially flat, oppositely disposed bottomside;

b) removing Silicon from a predetermined portion of the topside to generate trenches having V-shaped cross-sections and having first and second angled sidewalls defining the V-shaped cross-section, wherein each angled sidewall defining the V-shaped cross-section is a Silicon face having a 111 orientation;

c) forming a Gate on the topside;

d) forming a Source on the topside;

e) forming a two-dimensional electron gas in at least one sidewall;

f) depositing a dielectric layer over the at least one sidewall; and

g) forming Drain in the bottomside.