High efficiency computer floating point multiplier unit
A high-power-efficiency multiplier combines a standard floating-point multiplier with a power-of-two multiplier that performs multiplications by shifting operations without the need for floating-point multiplication circuitry. By selectively steering some operands to this power-of-two multiplier, substantial power savings may be realized. In one embodiment, multiplicands may be modified to work with the power-of-two multiplier introducing low errors that may be accommodated in pixel calculations.
1. A multiplier circuit system for multiplying floating-point numbers expressed as exponents and significands in an electronic computer comprising:
a floating-point multiplier circuit receiving floating-point multiplicands having a first significand length and outputting a floating-point product of the floating-point multiplicands;
a power-of-two multiplier circuit receiving at least one constrained floating-point multiplicand having a second significand length less than the first significand length and outputting a floating-point product only for a product including at least one constrained floating-point multiplicand; and
a selector circuit directing floating-point multiplicands including at least one constrained floating-point multiplicand to the power-of-two multiplier circuit and directing a floating-point multiplicand not including at least one constrained floating-point multiplicand to the floating-point multiplier circuit and outputting a floating-point from a corresponding one of the power-of-two multiplier circuit and floating-point multiplier circuit;
wherein the selector circuit receives floating-point multiplicands and modifies at least some floating-point multiplicands to be constrained floating-point multiplicands when the modification changes the value of the received floating-point multiplicands by less than a predetermined error value and directs the modified floating-point multiplicands to the power-of-two multiplier circuit as constrained floating-point multiplicands.
2. The multiplier circuit system of claim 1 wherein the constrained floating-point multiplicand must have a significand less than or equal to half a length of the floating-point multiplier significand.
3. The multiplier circuit system of claim 2 wherein the constrained floating-point multiplicand is only a number equal to an integer power-of-two or a sum of numbers each equal to a consecutive integer power-of-two.
4. The multiplier circuit system of claim 3 wherein the constrained floating-point multiplicand is only a number equal to an integer power-of-two or a sum of only two numbers each equal to a consecutive integer power-of-two.
5. The multiplier circuit system of claim 1 wherein the modification rounds the received multiplicand to a precision of the second significand length.
6. The multiplier circuit system of claim 5 wherein the rounding selects between rounding up and rounding down to reduce an amount of change to the received floating-point multiplicand in the modification.
7. The multiplier circuit system of claim 1 wherein the floating-point multiplicands include an exponent portion and a significand portion and wherein the floating-point multiplier includes a significand multiplier and the power-of-two multiplier circuit does not include a significand multiplier.
8. The multiplier circuit system of claim 1 wherein each of the floating-point multiplier and power-of-two multiplier accepts three inputs including two multiplicands and one addend and operates to multiply the two multiplicands and sums a resulting product with the addend.
9. The multiplier circuit system of claim 1 wherein each of the floating-point multiplier and power-of-two multiplier are synchronous circuits receiving a clock signal and wherein the power-of-two multiplier receives a slower clock signal than the floating-point multiplier.
10. The multiplier circuit system of claim 9 wherein each of the floating-point multiplier and power-of-two multiplier provide for multiplications of the multiplicands with substantially identical processing time.
11. The multiplier circuit system of claim 1 wherein the selector circuit further reduces power to the floating-point multiplier circuit when the multiplications are directed to the power-of-two multiplier circuit.
12. A graphic processor unit providing multiple graphic processing cores each incorporating the multiplier circuit system of claim 1 .
13. A portable electronic device providing an electronic computer having a processor for executing a stored program as powered by a battery wherein the electronic processor provides the multiplier circuit system of claim 1 .
14. A multiplier circuit system for multiplying floating-point numbers expressed as exponents and significands in an electronic computer comprising:
a floating-point multiplier circuit receiving floating-point multiplicands having a first significand length and outputting a floating-point product of the floating-point multiplicands:
a power-of-two multiplier circuit receiving at least one constrained floating-point multiplicand having a second significand length less than the first significand length and outputting a floating-point product only for a product including at least one constrained floating-point multiplicand; and
a selector circuit directing floating-point multiplicands including at least one constrained floating-point multiplicand to the power-of-two multiplier circuit and directing a floating-point multiplicand not including at least one constrained floating-point multiplicand to the floating-point multiplier circuit and outputting a floating-point from a corresponding one of the power-of-two multiplier circuit and floating-point multiplier circuit;
wherein the power-of-two multiplier circuit further includes a significand shifter shifting one multiplicand if the multiplicand is a sum of two numbers equal to powers-of-two.
15. The multiplier circuit system of claim 14 wherein the shift is one position to the right when the multiplicand is the sum of two numbers equal to consecutive powers-of-two.
16. A method of multiplying digital values employing a multiplier circuit system for an electronic computer having:
a floating-point multiplier circuit receiving floating-point multiplicands and outputting a floating-point product of the floating-point multiplicands;
a power-of-two multiplier circuit receiving constrained floating-point multiplicands and outputting a floating-point product of the constrained floating-point multiplicands when the constrained floating-point multiplicands include at least one multiplicand limited to a number equal to an integer power-of-two or a sum of two numbers each equal to an integer power-of-two; and
a selector circuit directing floating-point multiplicands received by the multiplier circuit system to one of the floating-point multiplier circuit and power-of-two multiplier circuit and directing a corresponding one of the floating-point products of the floating-point multiplier circuit and power-of-two multiplier circuit to an output from the multiplier circuit system, the method comprising the steps of:
(a) evaluating by the multiplier circuit the multiplicands to determine when at least one multiplicand is a number equal to an integer power-of-two or a sum of two numbers each equal to an integer power-of-two;
(b) when at least one multiplicand is a number equal to an integer power-of-two or a sum of two numbers each equal to an integer power-of-two, causing the selector circuit to direct both multiplications to the power-of-two multiplier; and
(c) multiplying multiplicands directed to the power-of-two multiplier by the power-of-two multiplier;
further including the step of causing the selector circuit to direct both multiplicands to the power-of-two multiplier when at least one multiplicand may be approximated by a number equal to an integer power-of-two or a sum of two numbers each equal to an integer power-of-two to within a predetermined error magnitude.
17. The method of claim 16 wherein the multiplicands are expressed as floating-point numbers using exponents and significands and step (c) does not multiply the significands.
18. The method of claim 16 including the step of reducing power to the floating-point multiplier at step (c).