IP Library Granted Patent US 9,412,699
Granted Patent B2
US 9,412,699 · App. 14/313,024 · Granted Aug 9, 2016

Semiconductor device having groove-shaped via-hole

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Quick Facts
Patent No.
US 9,412,699
App. No.
14/313,024
Granted
Aug 9, 2016
Kind
B2
Abstract

The semiconductor device has insulating films 40, 42 formed over a substrate 10 ; an interconnection 58 buried in at least a surface side of the insulating films 40, 42 ; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66 a having a pattern bent at a right angle; and buried conductors 70, 72 a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66 a . A groove-shaped via-hole 66 a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66 . Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Claims (125)

1. A semiconductor device comprising:

a substrate that includes four corners;

a first conductive layer formed above the substrate;

a first guard ring, that includes a first conductor, formed above the substrate; and

a second guard ring, that includes a second conductor, formed above the substrate,

wherein:

the first conductor is connected to the first conductive layer;

the second conductor is connected to the first conductive layer;

the second guard ring is surrounded by the first guard ring;

the first conductor includes a first part, a second part and a third part at each of the four corners;

the first part extends in a first direction;

the second part extends in a second direction that is different from the first direction in a plan view;

the third part extends in a third direction that is different from the first direction and the second direction in a plan view;

the first part is connected to the third part;

the second part is connected to the third part;

the second conductor includes a fourth part, a fifth part and a sixth part at each of the four corners;

the fourth part extends in a fourth direction;

the fifth part extends in a fifth direction that is different from the fourth direction in a plan view;

the sixth part extends in a sixth direction that is different from the fourth direction and the fifth direction in a plan view;

the fourth part is connected to the sixth part; and

the fifth part is connected to the sixth part.

2. The semiconductor device according to claim 1 ,

wherein the first direction is perpendicular to the second direction in a plan view.

3. The semiconductor device according to claim 1 ,

wherein:

an angle of the first direction from the third direction is larger than 90 degrees in a plan view; and

an angle of the third direction from the second direction is larger than 90 degrees in a plan view.

4. The semiconductor device according to claim 1 ,

further comprising a first insulating film formed above the substrate,

wherein:

the first guard ring includes a first groove-shaped via-hole in the first insulating film;

the second guard ring includes a second groove-shaped via-hole in the first insulating film;

the first conductor is formed in the first groove-shaped via-hole; and

the second conductor is formed in the second groove-shaped via-hole.

5. The semiconductor device according to claim 4 , wherein the first insulating film includes silicon, carbon and oxygen.

6. The semiconductor device according to claim 1 , wherein:

the first conductive layer includes copper;

the first conductor includes copper; and

the second conductor includes copper.

7. The semiconductor layer according to claim 1 , wherein

the first conductor includes a first tantalum based film and a first copper film; and

the second conductor includes a second tantalum based film and a second copper film.

8. The semiconductor device according to claim 1 , further comprising:

a first aluminum pattern formed above the first guard ring and electrically connected to the first guard ring.

9. The semiconductor device according to claim 1 , further comprising:

a first aluminum pattern formed above the first guard ring and connected to the first guard ring by a contact plug.

10. A semiconductor device comprising:

a substrate that includes four corners;

a first conductive layer formed above the substrate;

a first guard ring, that includes a first conductor, formed above the substrate; and

a second guard ring, that includes a second conductor, formed above the substrate,

wherein

the first conductor is connected to the substrate;

the second conductor is connected to the substrate;

the first conductor is connected to the first conductive layer

the second conductor is connected to the first conductive layer

the second guard ring is surrounded by the first guard ring;

the first conductor includes a first part, a second part and a third part at each of the four corners;

the first part extends in a first direction;

the second part extends in a second direction that is different from the first direction in a plan view;

the third part extends in a third direction that is different from the first direction and the second direction in a plan view;

the first part is connected to the third part;

the second part is connected to the third part;

the second conductor includes a fourth part, a fifth part and a sixth part at each of the four corners;

the fourth part extends in a fourth direction;

the fifth part extends in a fifth direction that is different from the fourth direction in a plan view;

the sixth part extends in a sixth direction that is different from the fourth direction and the fifth direction in a plan view;

the fourth part is connected to the sixth part; and

the fifth part is connected to the sixth part.

11. The semiconductor device according to claim 10 , wherein the first direction is perpendicular to the second direction in a plan view.

12. The semiconductor device according to claim 10 , wherein:

an angle of the first direction from the third direction is larger than 90 degrees in a plan view; and

an angle of the third direction from the second direction is larger than 90 degrees in a plan view.

13. The semiconductor device according to claim 10 , further comprising a first insulating film formed above the substrate, wherein:

the first guard ring includes a first groove-shaped via-hole in the first insulating film;

the second guard ring includes a second groove-shaped via-hole in the first insulating film;

the first conductor is formed in the first groove-shaped via-hole; and

the second conductor is formed in the second groove-shaped via-hole.

14. The semiconductor device according to claim 13 , wherein the first insulating film includes silicon and oxygen.

15. The semiconductor device according to claim 10 , wherein:

the first conductor includes tungsten; and

the second conductor includes tungsten.

16. The semiconductor device according to claim 10 , wherein:

the first conductor includes a first tungsten film and a first titanium nitride film; and

the second conductor includes a second tungsten film and a second titanium nitride film.

17. The semiconductor device according to claim 10 , further comprising:

a first aluminum pattern formed above the first guard ring and electrically connected to the first guard ring.

18. The semiconductor device according to claim 10 , further comprising:

a first aluminum pattern formed above the first guard ring and connected to the first guard ring by a contact plug.

19. The semiconductor device according to claim 1 , further comprising

a third guard ring, that includes a third conductor, formed above the substrate, and

a fourth guard ring, that includes a fourth conductor, formed above the substrate,

wherein

the third conductor is connected to the first conductive layer,

the fourth conductor is connected to the first conductive layer,

the third conductor includes a seventh part, an eighth part and a ninth part at each of the four corners;

the seventh part extends in a seventh direction;

the eighth part extends in an eighth direction that is different from the seventh direction in a plan view;

the ninth part extends in a ninth direction that is different from the seventh direction and the eighth direction in a plan view;

the seventh part is connected to the ninth part; and

the eighth part is connected to the ninth part.

20. The semiconductor device according to claim 19 , further comprising

a first aluminum pattern formed above the first guard ring, and

a second aluminum pattern formed above the third guard ring,

wherein:

the first guard ring is electrically connected to the first aluminum pattern, and

the third guard ring is electrically connected to the second aluminum pattern.

21. The semiconductor device according to claim 10 , further comprising

a third guard ring, that includes a third conductor, formed above the substrate, and

a fourth guard ring, that includes a fourth conductor, formed above the substrate,

wherein

the third conductor is connected to the first conductive layer,

the fourth conductor is connected to the first conductive layer,

the third conductor includes a seventh part, an eighth part and a ninth part at each of the four corners;

the seventh part extends in a seventh direction;

the eighth part extends in an eighth direction that is different from the seventh direction in a plan view;

the ninth part extends in a ninth direction that is different from the seventh direction and the eighth direction in a plan view;

the seventh part is connected to the ninth part; and

the eighth part is connected to the ninth part.

22. The semiconductor device according to claim 21 , further comprising

a first aluminum pattern formed above the first guard ring, and

a second aluminum pattern formed above the third guard ring,

wherein:

the first guard ring is electrically connected to the first aluminum pattern, and

the third guard ring is electrically connected to the second aluminum pattern.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035453/0904 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2014
From: WATANABE, KENICHI
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 033169/0157 →