SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A manufacturing method of a semiconductor device in which the threshold is adjusted to an appropriate value is provided. The semiconductor device includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is sandwiched, an electron trap layer between the first gate electrode and the semiconductor, and a gate insulating layer between the second gate electrode and the semiconductor. By keeping a potential of the first gate electrode higher than a potential of the source or drain electrode for 1 second or more while heating, electrons are trapped in the electron trap layer. Consequently, threshold is increased and Icut is reduced.
1 . A semiconductor device comprising:
a first gate electrode and a second gate electrode;
a semiconductor between the first gate electrode and the second gate electrode;
an electrode which is electrically connected to the semiconductor;
an electron trap layer between the first gate electrode and the semiconductor; and
a gate insulating layer between the second gate electrode and the semiconductor.
2 . The semiconductor device according to claim 1 , wherein the electron trap layer contains any one of hafnium oxide, aluminum oxide, tantalum oxide, and aluminum silicate.
3 . The semiconductor device according to claim 1 , wherein the electrode is either a source electrode or a drain electrode.
4 . The semiconductor device according to claim 1 , wherein the electron trap layer includes a conductive layer.
5 . The semiconductor device according to claim 1 , wherein the electron trap layer includes a first insulating layer between the semiconductor and the first gate electrode, and a second insulating layer between the first insulating layer and the first gate electrode.
6 . The semiconductor device according to claim 5 , wherein a band gap of the first insulating layer is larger than that of the second insulating layer.
7 . The semiconductor device according to claim 1 , wherein the electron trap layer includes a first insulating layer between the semiconductor and the first gate electrode, a second insulating layer between the first insulating layer and the first gate electrode, and a third insulating layer between the second insulating layer and the first gate electrode.
8 . The semiconductor device according to claim 7 , wherein a band gap of the third insulating layer is larger than that of the second insulating layer.
9 . A semiconductor device comprising:
a first gate electrode and a second gate electrode;
a first semiconductor between the first gate electrode and the second gate electrode;
an electrode which is electrically connected to the first semiconductor,
a second semiconductor between the first semiconductor and the first gate electrode;
a third semiconductor between the first semiconductor and the second gate electrode,
an electron trap layer between the first gate electrode and the second semiconductor; and
a gate insulating layer between the second gate electrode and the third semiconductor.
10 . The semiconductor device according to claim 9 , wherein the electron trap layer contains any one of hafnium oxide, aluminum oxide, tantalum oxide, and aluminum silicate.
11 . The semiconductor device according to claim 9 , wherein the electrode is either a source electrode or a drain electrode.
12 . The semiconductor device according to claim 9 , wherein the electron trap layer includes a conductive layer.
13 . The semiconductor device according to claim 9 , wherein the electron trap layer includes a first insulating layer between the second semiconductor and the first gate electrode, and a second insulating layer between the first insulating layer and the first gate electrode.
14 . The semiconductor device according to claim 13 , wherein a band gap of the first insulating layer is larger than that of the second insulating layer.
15 . The semiconductor device according to claim 9 , wherein the electron trap layer includes a first insulating layer between the second semiconductor and the first gate electrode, a second insulating layer between the first insulating layer and the first gate electrode, and a third insulating layer between the second insulating layer and the first gate electrode.
16 . The semiconductor device according to claim 15 , wherein a band gap of the third insulating layer is larger than that of the second insulating layer.
17 . The semiconductor device according to claim 9 , wherein the first semiconductor, the second semiconductor, and the third semiconductor are oxide semiconductor layers.
18 . A manufacturing method of a semiconductor device comprising:
forming a first gate electrode;
forming a first insulating layer over the first gate electrode;
forming a semiconductor over the first insulating layer;
forming an electrode which is electrically connected to the semiconductor,
forming a second insulating layer over the semiconductor,
forming a second gate electrode over the second insulating layer; and
keeping a potential of the first gate electrode higher than a potential of the electrode for one second or longer at a temperature higher than or equal to 125° C. and lower than or equal to 450° C.
19 . The manufacturing method of the semiconductor device, according to claim 18 , wherein a potential applied to the first gate electrode is lower than a highest potential used in the semiconductor device and higher than 1 V.
20 . The manufacturing method of the semiconductor device, according to claim 18 , wherein the first insulating layer contains any one of hafnium oxide, aluminum oxide, tantalum oxide, and aluminum silicate.
21 . The manufacturing method of the semiconductor device, according to claim 18 , wherein the electrode is either a source electrode or a drain electrode.
22 . The manufacturing method of the semiconductor device, according to claim 18 , wherein the first insulating layer includes a third insulating layer and a fourth insulating layer over the third insulating layer.
23 . The manufacturing method of the semiconductor device, according to claim 18 , wherein the first insulating layer includes a third insulating layer, a fourth insulating layer over the third insulating layer, and a fifth insulating layer over the fourth insulating layer.
24 . The manufacturing method of the semiconductor device, according to claim 18 , wherein the semiconductor includes a first semiconductor, a second semiconductor over the first semiconductor, and a third semiconductor over the second semiconductor.
25 . The manufacturing method of the semiconductor device, according to claim 24 , wherein the first semiconductor, the second semiconductor, and the third semiconductor are oxide semiconductor layers.