Semiconductor device having a reduced footprint of wires connecting a DLL circuit with an input/output buffer
An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in response to the external clock signal, first and second output circuits each coupled to the clock generator, a first clock line coupled between the clock generator and the first output circuit, and the second clock line coupled between the clock generator and the second output circuit. The first clock line represents a first capacitance and a first resistance while the second clock line represents a second capacitance and a second resistance. A first value defined as the product of the first capacitance and the first resistance is substantially equal to a second value defined as the product of the second capacitance and the second resistance.
1. An apparatus comprising:
a clock terminal configured to receive an external clock signal;
a clock generator coupled to the clock terminal and configured to generate an internal clock signal in response to the external clock signal;
a main clock line coupled to the clock generator at a first portion, the main clock line further includes a second portion and a third portion that is between the first and second portion;
first and second output circuits arranged along the main clock line;
a first clock line coupled to the third portion of the main clock line at one end thereof and coupled to the first output circuit at the other end thereof; and
a second clock line coupled to the second portion of the main clock line at one end thereof and coupled to the second output circuit at the other end thereof, the first clock line is greater in length than the second clock line and the capacitance-resistance (CR) time constants of the first and second clock lines are substantially equal.
2. The apparatus as claimed in claim 1 , wherein the main clock line elongates straightly in line.
3. The apparatus as claimed in claim 1 , wherein the clock generator includes a DLL circuit.
4. An apparatus comprising:
a clock terminal configured to receive an external clock signal;
a clock generator coupled to the clock terminal and configured to generate an internal clock signal in response to the external clock signal;
a main clock line coupled to the clock generator at a first portion, the main clock line further includes a second portion and a third portion that is between the first and second portion;
first and second output circuits arranged along the main clock line;
a first clock line coupled to the third portion of the main clock line at one end thereof and coupled to the first output circuit at the other end thereof; and
a second clock line coupled to the second portion of the main clock line at one end thereof and coupled to the second output circuit at the other end thereof, the first clock line is greater in length than the second clock line, wherein the first clock line includes a first resistor and the second clock line includes a second resistor that is smaller in resistance value than the first resistor.
5. An apparatus comprising:
a clock terminal configured to receive an external clock signal;
a clock generator coupled to the clock terminal and configured to generate an internal clock signal in response to the external clock signal;
a main clock line coupled to the clock generator at a first portion, the main clock line further includes a second portion and a third portion that is between the first and second portion;
first and second output circuits arranged along the main clock line;
a first clock line coupled to the third portion of the main clock line at one end thereof and coupled to the first output circuit at the other end thereof; and
a second clock line coupled to the second portion of the main clock line at one end thereof and coupled to the second output circuit at the other end thereof, the first clock line is greater in length than the second clock line, wherein each of the first and second clock lines includes an adjustable resistor.
6. An apparatus comprising:
a clock terminal configured to receive an external clock signal;
a clock generator coupled to the clock terminal and configured to generate an internal clock signal in response to the external clock signal;
a main clock line coupled to the clock generator at a first portion, the main clock line further includes a second portion and a third portion that is between the first and second portion;
first and second output circuits arranged along the main clock line;
a first clock line coupled to the third portion of the main clock line at one end thereof and coupled to the first output circuit at the other end thereof; and
a second clock line coupled to the second portion of the main clock line at one end thereof and coupled to the second output circuit at the other end thereof, the first clock line is greater in length than the second clock line, wherein the first clock line includes a first capacitor and the second clock line includes a second capacitor that is smaller in capacitance value than the first capacitor.
7. An apparatus comprising:
a clock terminal configured to receive an external clock signal;
a clock generator coupled to the clock terminal and configured to generate an internal clock signal in response to the external clock signal;
a main clock line coupled to the clock generator at a first portion, the main clock line further includes a second portion and a third portion that is between the first and second portion;
first and second output circuits arranged along the main clock line;
a first clock line coupled to the third portion of the main clock line at one end thereof and coupled to the first output circuit at the other end thereof;
a second clock line coupled to the second portion of the main clock line at one end thereof and coupled to the second output circuit at the other end thereof, the first clock line is greater in length than the second clock line; and
a multi-level wiring structure including a first wiring layer, a second wiring layer formed above the first wiring layer and a third wiring layer formed above the second wiring layer, and wherein the main clock line is formed as the third wiring layer, each of the first and second clock lines includes a first line portion that is formed as the first wiring layer, a second line portion that is formed as the second wiring layer and a third line portion that is formed as the third wiring layer.
8. The apparatus as claimed in claim 7 , wherein the second line portion of the first clock line is coupled to the first output circuit, the third line portion of the first clock line is coupled to the main clock line, the first line portion of the first clock line is coupled between the second and third line portions of the first clock line, the third line portion of the second clock line is coupled to the main clock line, the second line portion of the second clock line is coupled to the second output circuit, and the first line portion of the second clock line is coupled between the second and third line portions of the second clock line.
9. The apparatus as claimed in claim 7 , wherein the first line portion of the first clock line is greater in length than the first line portion of the second clock line.
10. The apparatus as claimed in claim 7 , wherein the first wiring layer includes a tungsten layer.
11. An apparatus comprising:
a clock terminal configured to receive an external clock signal;
a clock generator coupled to the clock terminal and configured to generate an internal clock signal in response to the external clock signal;
first and second output circuits each coupled to the clock generator;
a first clock line coupled to the clock generator at one end thereof and coupled to the first output circuit at the other end thereof to convey the internal clock signal from the clock generator to the first output circuit, the first clock line representing a first capacitance and a first resistance; and
a second clock line coupled to the clock generator at one end thereof and coupled to the second output circuit at the other end thereof to convey the internal clock signal from the clock generator to the second output circuit, the second clock line representing a second capacitance that is different from the first capacitance and a second resistance that is different from the first resistance,
wherein a first value defined as the product of the first capacitance and the first resistance is substantially equal to a second value defined as the product of the second capacitance and the second resistance.
12. The apparatus as claimed in claim 11 , wherein the first clock line is different in length from the second clock line.
13. The apparatus as claimed in claim 11 , wherein the first clock line includes a first resistor, the second clock line includes a second resistor and the first resistor is different in resistance from the second resistor.
14. The apparatus as claimed in claim 13 , further comprising a semiconductor substrate and a first wiring layer located above the semiconductor substrate, and wherein each of the first and second resistors is formed as the first wiring layer.
15. The apparatus as claimed in claim 11 , wherein the first clock line includes a first part, the second clock line includes a second part, and the first part of the first clock line and the second part of the second clock line are formed as a common clock line.
16. The apparatus as claimed in claim 15 , further comprising a multi-level wiring structure including a first wiring layer and a second wiring layer formed above the first wiring layer, and wherein the common clock line is formed as the second wiring layer, the first clock line includes a first resistor, the second clock line includes a second resistor that is different in resistance from the first resistor, and each of the first and second resistors is formed as the first wiring layer.
17. The apparatus as claimed in claim 11 , wherein each of the first and second clock lines includes an adjustable resistor.
18. The apparatus as claimed in claim 11 , wherein the first clock line includes a first capacitor, the second clock line includes a second capacitor and the first capacitor is different in capacitance from the second capacitor.
19. The apparatus as claimed in claim 11 , further comprising a memory cell array, and wherein each of the first and second output circuits includes a multiplexer circuit coupled to the memory cell array and operates in response to the internal clock signal.
20. The apparatus as claimed in claim 11 , wherein the clock generator includes DLL circuit.