Statistical optimization in place-and-route
Place-and-route (P&R) includes maintaining a set of local arrival time information and local required time information associated with a circuit layout; determining a candidate fix on a critical path in the circuit layout; statistically determining, using one or more computer processors, a set of one or more adjusted local slacks associated with a region affected by the candidate fix; and in the event that the set of one or more adjusted local slacks indicates that the candidate fix results in a timing improvement, accepting the candidate fix.
1. A method comprising:
maintaining a set of local arrival time information and local required time information associated with a circuit layout;
determining a candidate fix on a critical path in the circuit layout;
determining an affected circuit portion that is affected by the candidate fix, wherein the affected circuit portion includes an affected path or a portion of an affected path that has a timing-related value that is changed due to the candidate fix, and that the change in the timing-related value due to the candidate fix exceeds a threshold;
statistically determining a set of one or more adjusted local slacks associated with the affected circuit portion, wherein the set of one or more adjusted local slacks associated with the affected circuit portion is statistically determined based on one or more of: a variance of an arrival time associated with the affected circuit portion, a variance of a required time associated with the affected circuit portion, or a variance of a Clock Re-convergence Pessimism Removal (CRPR) time associated with the affected circuit portion; and
in the event that the set of one or more adjusted local slacks indicates that the candidate fix results in a timing improvement, accepting the candidate fix.
2. The method of claim 1 , wherein statistically determining the set of one or more adjusted local slacks associated with the affected circuit portion includes identifying the affected path or the portion of the affected path.
3. The method of claim 1 , wherein the timing-related value includes a slack value.
4. The method of claim 1 , wherein the timing-related value includes a capacitance value.
5. The method of claim 1 , wherein the set of one or more adjusted local slacks associated with the affected circuit portion is determined based at least in part on a set of one or more local arrival times and a set of one or more local required times resulting from the candidate fix.
6. The method of claim 1 , wherein the affected circuit portion includes a portion of the critical path that is in proximity to the candidate fix.
7. The method of claim 1 , wherein the affected circuit portion includes a portion of a fanout path that fans out from the candidate fix.
8. The method of claim 1 , wherein the affected circuit portion includes a portion of an unconnected path whose timing is affected by the candidate fix.
9. The method of claim 1 , wherein an adjusted local slack associated with the affected circuit portion is statistically determined based at least in part on mean values and variance values of cell delays.
10. A system comprising:
one or more processors configured to:
maintain a set of local arrival time information and local required time information associated with a circuit layout;
determine a candidate fix on a critical path in the circuit layout;
determine an affected circuit portion that is affected by the candidate fix, wherein the affected circuit portion includes an affected path or a portion of an affected path that has a timing-related value that is changed due to the candidate fix, and that the change in the timing-related value due to the candidate fix exceeds a threshold;
statistically determine a set of one or more adjusted local slacks associated with the affected circuit portion, wherein the set of one or more adjusted local slacks associated with the affected circuit portion is statistically determined based on one or more of: a variance of an arrival time associated with the affected circuit portion, a variance of a required time associated with the affected circuit portion, or a variance of a Clock Re-convergence Pessimism Removal (CRPR) time associated with the affected circuit portion; and
in the event that the set of one or more adjusted local slacks indicates that the candidate fix results in a timing improvement, accept the candidate fix; and
one or more memories coupled to the one or more processors and configured to provide the one or more processors with instructions.
11. The system of claim 10 , wherein to statistically determine the set of one or more adjusted local slacks associated with the affected circuit portion includes to identify the affected path or the portion of the affected path.
12. The system of claim 10 , wherein the timing-related value includes a slack value.
13. The system of claim 10 , wherein the timing-related value includes a capacitance value.
14. The system of claim 10 , wherein the set of one or more adjusted local slacks associated with the affected circuit portion is determined based at least in part on a set of one or more local arrival times and a set of one or more local required times resulting from the candidate fix.
15. The system of claim 10 , wherein the affected circuit portion includes a portion of the critical path that is in proximity to the candidate fix.
16. The system of claim 10 , wherein the affected circuit portion includes a portion of a fanout path that fans out from the candidate fix.
17. The system of claim 10 , wherein the affected circuit portion includes a portion of an unconnected path whose timing is affected by the candidate fix.
18. The system of claim 10 , wherein an adjusted local slack associated with the affected circuit portion is statistically determined based at least in part on mean values and variance values of cell delays.
19. A computer program product embodied in a non-transitory computer readable storage medium and comprising computer instructions for:
maintaining a set of local arrival time information and local required time information associated with a circuit layout;
determining a candidate fix on a critical path in the circuit layout;
determining an affected circuit portion that is affected by the candidate fix, wherein the affected circuit portion includes an affected path or a portion of an affected path that has a timing-related value that is changed due to the candidate fix, and that the change in the timing-related value due to the candidate fix exceeds a threshold;
statistically determining a set of one or more adjusted local slacks associated with the affected circuit portion, wherein the set of one or more adjusted local slacks associated with the affected circuit portion is statistically determined based on one or more of: a variance of an arrival time associated with the affected circuit portion, a variance of a required time associated with the affected circuit portion, or a variance of a Clock Re-convergence Pessimism Removal (CRPR) time associated with the affected circuit portion; and
in the event that the set of one or more adjusted local slacks indicates that the candidate fix results in a timing improvement, accepting the candidate fix.
20. The method of claim 1 , wherein the affected circuit portion for which the set of one or more adjusted local slacks is determined is included in the critical path.