Method and structure for straining carrier channel in vertical gate all-around device
Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region ( 140 ); a drain region ( 190 ) aligned substantially vertically to the source region; a channel structure ( 160 ) bridging between the source region and the drain region and defining a substantially vertical channel direction; and a gate structure ( 170 ) arranged vertically between the source region and the drain region and surrounding the channel structure. The channel structure comprises a plurality of channels ( 161 ) extending substantially vertically abreast each other, each bridging the source region and the drain region, and at least one stressor ( 240 ) interposed between each pair of adjacent channels and extending substantially along the vertical channel direction; the stressor affects lateral strain on the adjacent channels, thereby straining the channels in the vertical channel direction.
1. A semiconductor device, comprising:
a source region;
a drain region aligned substantially vertically to the source region;
a channel structure bridging the source region and the drain region, the channel structure comprising:
at least one channel portion defining a substantially vertical channel direction, and
at least one stressor disposed adjacent to the channel portion and extending substantially along the vertical channel direction; and
a gate structure arranged vertically between the source region and the drain region and surrounding the channel structure;
wherein the stressor affects lateral strain on the adjacent channel portion, thereby straining the channel portion in the vertical channel direction.
2. The device of claim 1 , wherein the channel structure comprises a nanobar defining a lateral length, a lateral width, and a vertical height.
3. The device of claim 2 , wherein the length of the nanobar is in the range of about 1 nm to about 1 um, the width thereof is in the range of about 1 nm to about 50 nm, and the height thereof is in the range of about 1 nm to about 100 nm.
4. The device of claim 1 , wherein the stressor has a stressor length in the range of about 1 nm to about 100 nm, and a stressor width substantially matches the width of the channel structure.
5. The device of claim 1 , which comprises a plurality of stressors, wherein the plurality of stressors are substantially evenly disposed along the lateral length of the channel structure.
6. The device of claim 1 , wherein the stressor provides a lateral compressive strain, thereby causing vertical tensile strain in the channel portion.
7. The device of claim 1 , wherein the stressor provides a lateral tensile strain, thereby causing vertical compression strain in the channel portion.
8. A strained structure for improving carrier mobility in a vertical gate all-around semiconductor device, comprising:
a channel structure bridging a source and a drain regions of the semiconductor device, comprising:
at least one channel portion defining a substantially vertical channel direction; and
at least one stressor disposed adjacent to the channel portion and extending substantially along the vertical channel direction,
wherein the stressor affects lateral strain on the adjacent channel portion, thereby straining the channel portion in the vertical direction.
9. The structure of claim 8 , wherein the channel structure comprises a nanobar defining a lateral length, a lateral width, and a vertical height.
10. The structure of claim 9 , wherein the length of the nanobar is in the range of about 1 nm to about 1 um, the width thereof is in the range of about 1 nm to about 50 nm, and the height thereof is in the range of about 1 nm to about 100 nm.
11. The structure of claim 9 , wherein the stressor has a stressor length in the range of about 1 nm to about 100 nm, and a stressor width substantially matches the width of the channel structure.
12. The structure of claim 9 , which comprises a plurality of stressors, wherein the plurality of stressors are substantially evenly disposed along the lateral length of the channel structure.
13. The structure of claim 9 , wherein the stressor provides a lateral compressive strain, thereby causing vertical tensile strain in the channel portion.
14. The structure of claim 9 , wherein the stressor provides a lateral tensile strain, thereby causing vertical compression strain in the channel portion.
15. A semiconductor device, comprising:
a channel structure of the semiconductor device comprising:
at least one channel portion defining a substantially vertical channel direction, and
at least one stressor disposed adjacent to the channel portion and extending substantially along the vertical channel direction, the stressor straining the channel portion in the vertical channel direction; and
a gate structure surrounding the channel structure.
16. The semiconductor device of claim 15 , wherein the channel structure comprises a nanobar defining a lateral length, a lateral width, and a vertical height.
17. The semiconductor device of claim 16 , wherein the stressor has a stressor length in the range of about 1 nm to about 100 nm, and a stressor width substantially matches the width of the channel structure.
18. The semiconductor device of claim 16 , wherein the at least one stressor comprises a plurality of stressors, and wherein the plurality of stressors are substantially evenly spaced along the lateral length of the channel structure.
19. The semiconductor device of claim 15 , wherein the stressor provides a lateral compressive strain, thereby causing vertical tensile strain in the channel portion.
20. The semiconductor device of claim 15 , wherein the stressor provides a lateral tensile strain, thereby causing vertical compression strain in the channel portion.