Gate structure having spacer with flat top surface and method for forming the same

1. A semiconductor structure, comprising:

a first gate structure formed over a substrate;

a first spacer formed on a sidewall of the first gate structure, wherein a top surface of the first spacer is parallel to a top surface of the substrate;

a source and drain structure formed in the substrate adjacent to the first spacer;

a first contact formed on the source and drain structure, wherein a portion of the first contact is in direct contact with the top surface of the first spacer; and

a contact etch stop layer along an outer sidewall of the first spacer, wherein the outer sidewall of the first spacer is separate from the first contact by the contact etch stop layer, and another portion of the first contact is in direct contact with a top and an outer sidewall of the contact etch stop layer,

wherein the top surface of the first spacer is level with a top surface of a gate electrode layer of the first gate structure.

2. The semiconductor structure as claimed in claim 1 , wherein a top of the contact etch stop layer is not above the top surface of the first spacer.

3. The semiconductor structure as claimed in claim 1 , wherein the first spacer has two straight sidewalls vertical with a top surface of the substrate.

4. The semiconductor structure as claimed in claim 1 , wherein the first spacer is in a shape of a rectangle.

5. The semiconductor structure as claimed in claim 1 , wherein the top surface of the first spacer has a first width in a range from about 7 nm to about 10 nm.

6. The semiconductor structure as claimed in claim 1 , wherein the top surface of the first spacer has a first width and a bottom surface of the first spacer has a second width the same as the first width.

7. The semiconductor structure as claimed in claim 1 , wherein the source and drain structure is a strained source and drain structure.

8. The semiconductor structure as claimed in claim 1 , wherein the first gate structure comprises a high-k dielectric layer, a metal work function layer, and a metal gate electrode layer.

9. A semiconductor structure, comprising:

a first gate structure and a second gate structure formed over a substrate;

a first spacer formed on a sidewall of the first gate structure and a second spacer formed on a sidewall of the second gate structure;

a first source and drain structure formed in the substrate adjacent to the first spacer and a second source and drain structure formed in the substrate adjacent to the second spacer;

a first contact formed on the first source and drain structure and a second contact formed on the second source and drain structure, wherein a top surface of the first spacer is parallel to a top surface of the substrate, and a portion of the first contact is in direct contact with the top surface of the first spacer;

a first contact formed on the first source and drain structure, wherein a portion of the first contact is in direct contact with the top surface of the first spacer; and

a first contact etch stop layer along an outer sidewall of the first spacer, wherein the outer sidewall of the first spacer is separate from the first contact by the first contact etch stop layer, and another portion of the first contact is in direct contact with a top and an outer sidewall of the first contact etch stop layer,

wherein the top surface of the first spacer is level with a top surface of a gate electrode layer of the first gate structure.

10. The semiconductor structure as claimed in claim 9 , wherein a top surface of the second spacer is parallel to a top surface of the substrate, and the second contact is not in direct contact with the top surface of the second spacer.

11. The semiconductor structure as claimed in claim 9 , wherein the first contact is overlapped with the first spacer and the second contact is not overlapped with the second spacer.

12. The semiconductor structure as claimed in claim 9 , wherein the first spacer and the second spacer are respectively in a shape of a rectangle.

13. The semiconductor structure as claimed in claim 9 , wherein the top surface of the first spacer has a first width in a range from about 7 nm to about 10 nm.

14. The semiconductor structure as claimed in claim 9 , wherein the first gate structure comprises a P-type metal work function layer, and the second gate structure comprises a N-type metal work function layer.

15. A method for forming a semiconductor structure, comprising:

forming a first dummy gate structure over a substrate;

forming a dielectric layer to cover the first dummy gate structure over the substrate;

performing an etching process to form a rectangular first spacer on a sidewall of the first dummy gate structure;

forming a first source and drain structure in the substrate adjacent to the rectangular first spacer;

after the step of performing the etching process to form the rectangular first spacer on the sidewall of the first dummy gate structure, forming a first contact etch stop layer along an outer sidewall of the first spacer and level with a top surface of the first spacer;

after the steps of forming the first spacer and forming the first contact etch stop layer along the outer sidewall of the first spacer and level with the top surface of the first spacer, replacing the first dummy gate structure by a first gate structure such that the top surface of the first spacer is level with a top surface of a gate electrode layer of the first gate structure; and

forming a first contact connected to the first source and drain structure such that a portion of the first contact is in direct contact with the top surface of the first spacer, the outer sidewall of the first spacer is separate from the first contact by the first contact etch stop layer, and another portion of the first contact is in direct contact with a top and an outer sidewall of the first contact etch stop layer.

16. The method for forming a semiconductor structure as claimed in claim 15 , wherein the rectangular first spacer is etched by a dry etching process.

17. The method for forming a semiconductor structure as claimed in claim 15 , wherein the etching process comprises using an etching gas, and the etching gas comprises helium (He), argon (Ar), hydrogen bromide (HBr), nitrogen (N2), methane (CH4), tetrafluoromethane (CF4), monofluoromethane (CH3F), difluoromethane (CH2F2), trifluoromethane (CHF3), oxygen (O2), or a combination thereof.

18. The method for forming a semiconductor structure as claimed in claim 15 , wherein a top surface of the rectangular spacer has a first width in a range from 7 nm to about 10 nm.

19. The method for forming a semiconductor structure as claimed in claim 15 , further comprising:

forming a second dummy gate structure over the substrate;

forming the dielectric layer to cover the second dummy gate structure over the substrate;

performing the etching process to form a rectangular second spacer on a sidewall of the second dummy gate structure;

forming a second source and drain structure in the substrate adjacent to the rectangular second spacer;

replacing the second dummy gate structure by a second gate structure; and

forming a second contact connected to the second source and drain structure.

20. The method for forming a semiconductor structure as claimed in claim 19 , wherein a top surface of the first spacer is parallel to a top surface of the substrate, while a top surface of the second spacer is parallel to the top surface of the substrate and the second contact is not in direct contact with the top surface of the second spacer.