Accelerating boot time zeroing of memory based on non-volatile memory (NVM) technology

1. An apparatus comprising:

a storage device to store a boot version number corresponding to a portion of a non-volatile memory; and

memory controller logic, coupled to the non-volatile memory, to cause an update of the stored boot version number in response to each subsequent boot event,

wherein the memory controller logic is to return a zero in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number, wherein the portion of the non-volatile memory is to store metadata, wherein the metadata is to comprise a saved version number and a zero bit per sub-portion of the portion of the non-volatile memory.

2. The apparatus of claim 1 , wherein the memory controller logic is to return the zero in response to the read operation directed at the portion of the non-volatile memory and the mismatch between the stored boot version number and the current boot version number without accessing the portion of the non-volatile memory.

3. The apparatus of claim 1 , wherein the memory controller logic is to cause the update of the boot version number in response to a write operation to the portion of the non-volatile memory.

4. The apparatus of claim 1 , wherein the current boot version number corresponds to an in-process boot event.

5. The apparatus of claim 1 , wherein the memory controller logic is to cause the update of the boot version number by incrementing the boot version number.

6. The apparatus of claim 1 , comprising refresh engine logic to continuously scrub each line of the non-volatile memory based on a reference address counter, wherein the reference address counter is to point to a line of the non-volatile memory to be scrubbed.

7. The apparatus of claim 6 , wherein the reference address counter is to be updated in response to scrubbing of a corresponding line of the non-volatile memory.

8. The apparatus of claim 6 , wherein the refresh engine logic is to perform a refresh cycle based on a pre-determined interval.

9. The apparatus of claim 6 , wherein the refresh engine logic is to perform a refresh cycle based on a refresh version number.

10. The apparatus of claim 1 , wherein the memory controller logic is to refrain from using the stored boot version number prior to a completion of a refresh cycle based on data stored in a current version refresh state table.

11. The apparatus of claim 1 , wherein the portion of the non-volatile memory is to comprise a memory line and the sub-portion is to comprise a sub-line.

12. The apparatus of claim 1 , wherein the memory line is to comprise four sub-lines.

13. The apparatus of claim 1 , wherein the non-volatile memory is to comprise three dimensional cross point memory.

14. The apparatus of claim 1 , wherein the non-volatile memory is to comprise the storage device.

15. The apparatus of claim 1 , wherein one or more processor cores are coupled to the memory controller logic to access data stored in the non-volatile memory.

16. The apparatus of claim 1 , wherein one or more of the memory controller logic, one or more processor cores, the storage device, and the non-volatile memory are on a same integrated circuit die.

17. The apparatus of claim 1 , wherein the portion of the non-volatile memory is to comprise 256 bytes.

18. A method comprising:

storing, in a storage device, a boot version number corresponding to a portion of a non-volatile memory; and

causing an update of the stored boot version number in response to each subsequent boot event,

wherein a zero is returned in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number, wherein the portion of the non-volatile memory stores metadata, wherein the metadata comprises a saved version number and a zero bit per sub-portion of the portion of the non-volatile memory.

19. The method of claim 18 , wherein the zero is returned in response to the read operation directed at the portion of the non-volatile memory and the mismatch between the stored boot version number and the current boot version number without accessing the portion of the non-volatile memory.

20. The method of claim 18 , further comprising causing the update of the boot version number in response to a write operation to the portion of the non-volatile memory.

21. A non-transitory computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:

store, in a storage device, a boot version number corresponding to a portion of a non-volatile memory; and

cause an update of the stored boot version number in response to each subsequent boot event,

wherein a zero is returned in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number, wherein the portion of the non-volatile memory store metadata, wherein the metadata comprises a saved version number and a zero bit per sub-portion of the portion of the non-volatile memory.

22. The computer-readable medium of claim 21 , further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause the zero to be returned in response to the read operation directed at the portion of the non-volatile memory and the mismatch between the stored boot version number and the current boot version number without accessing the portion of the non-volatile memory.

23. The computer-readable medium of claim 21 , further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause the update of the boot version number in response to a write operation to the portion of the non-volatile memory.