Thin film transistor, method of manufacturing the same, and electronic apparatus
A thin film transistor includes: a gate electrode and a pair of source and drain electrodes; and a semiconductor layer having a channel formed therein, and having a pair of connection sections connected to the pair of source and drain electrodes, respectively, wherein one or both of opposed surfaces of the pair of connection sections is a non-flat surface.
1. A thin film transistor, comprising:
a gate electrode and a pair of source and drain electrodes; and
a semiconductor layer having a channel formed therein, and having a pair of connection sections connected to the pair of source and drain electrodes, respectively,
wherein one or both of opposed surfaces of the pair of connection sections is a non-flat surface,
wherein a cross section of each of the connection sections has a concavo-convex shape,
wherein each of the connection sections forms a wall surface of a through-hole penetrating the entire thickness of the semiconductor layer, the entire thickness of a first insulating layer and at least a portion of thickness of a second insulating layer,
wherein the first insulating layer is provided between the semiconductor layer and the pair of source and drain electrodes, and
wherein the second insulating layer is provided between the semiconductor layer and the gate electrode.
2. The thin film transistor according to claim 1 , wherein the concavo-convex shape is one of a comb shape, a rounding shape, a sawtooth shape, a wave shape, and a lens array shape.
3. The thin film transistor according to claim 1 , wherein the wall surface of the through-hole has a tapered shape in at least the semiconductor layer.
4. The thin film transistor according to claim 1 , wherein the semiconductor layer is formed of one of low-temperature poly-silicon, an oxide semiconductor material, and an organic semiconductor material.
5. The thin film transistor according to claim 1 , wherein the semiconductor layer is provided between the gate electrode and the source and drain electrodes.
6. The thin film transistor according to claim 1 , wherein the pair of source and drain electrodes are provided between the gate electrode and the semiconductor layer.
7. A method of manufacturing a thin film transistor, the method comprising:
forming a gate electrode on a substrate;
forming a semiconductor layer on the substrate and the gate electrode;
forming a first insulating layer on the semiconductor layer;
forming a through-hole penetrating the entire thickness of the semiconductor layer, the entire thickness of the first insulating layer and at least a portion of thickness of a second insulating layer, wherein the second insulating layer is provided between the semiconductor layer and the gate electrode;
forming a pair of connection sections having opposed surfaces one or both of which is a non-flat surface, wherein a cross section of each of the connection sections has a concavo-convex shape,
wherein each of the connection sections forms a wall surface of the through-hole; and
forming a pair of source and drain electrodes on the semiconductor layer and the first insulating layer, the source and drain electrodes being to be connected to the semiconductor layer via the connection sections.
8. The method according to claim 7 , wherein the connection sections are formed by dry etching.
9. The method according to claim 7 , wherein the semiconductor layer is provided between the gate electrode and the source and drain electrodes.
10. The method according to claim 7 , wherein the pair of source and drain electrodes are provided between the gate electrode and the semiconductor layer.
11. An electronic apparatus provided with a display unit, the display unit being provided with a plurality of display devices and a plurality of thin film transistors configured to drive the display devices, each of the thin film transistors comprising:
a gate electrode and a pair of source and drain electrodes; and
a semiconductor layer having a channel formed therein, and having a pair of connection sections connected to the pair of source and drain electrodes, respectively,
wherein one or both of opposed surfaces of the pair of connection sections is a non-flat surface,
wherein a cross section of each of the connection sections has a concavo-convex shape,
wherein each of the connection sections forms a wall surface of a through-hole penetrating the entire thickness of the semiconductor layer, the entire thickness of a first insulating layer and at least a portion of thickness of a second insulating layer,
wherein the insulating layer is provided between the semiconductor layer and the pair of source and drain electrodes, and
wherein the second insulating layer is provided between the semiconductor layer and the gate electrode.