Redistribution layer contacting first wafer through second wafer
View Patent ↗A semiconductor structure is formed with first and second semiconductor wafers and a redistribution layer. The first semiconductor wafer is formed with a first active layer and a first interconnect layer. The second semiconductor wafer is formed with a second active layer and a second interconnect layer. The second semiconductor wafer is inverted and bonded to the first semiconductor wafer, and a substrate is removed from the second semiconductor wafer. The redistribution layer redistributes electrical connective pad locations on a side of the second semiconductor wafer. The redistribution layer also electrically contacts the first interconnect layer through a hole in the second active layer and the second interconnect layer.
1. An integrated circuit package comprising:
a first semiconductor wafer portion having a first plurality of active devices in a first active device layer, a first interconnect layer having a first plurality of conductive structures in communication with the first plurality of active devices, and a first insulator layer disposed between the first active device layer and a substrate layer of the first semiconductor wafer portion; and
a second semiconductor wafer portion bonded face-to-face with the first semiconductor wafer portion, the second semiconductor wafer portion having a second plurality of active devices in a second active device layer and having a second plurality of conductive structures in communication with the second plurality of active devices, the second semiconductor wafer portion further having a redistribution layer electrically coupling the first plurality of conductive structures with the second plurality of conductive structures, the redistribution layer including a metal layer having a horizontal extent from a first conductive bump to a second conductive bump, wherein the first conductive bump and the second conductive bump are disposed on the redistribution layer at the back side of the second semiconductor wafer portion.
2. The integrated circuit package of claim 1 , wherein the redistribution layer extends horizontally under the second plurality of active devices and extends vertically from a front surface of the second semiconductor wafer portion to under the second active device layer.
3. The integrated circuit package of claim 1 , wherein the redistribution layer extends vertically from a front surface of the second semiconductor wafer portion to under the second active device layer.