Integrated III-nitride D-mode HFET with cascoded pair half bridge
View Patent ↗There are disclosed herein various implementations of a group III-V power conversion circuit including a monolithically integrated half bridge having a depletion mode III-Nitride field-effect transistor (FET), and a normally OFF composite cascoded switch including a depletion mode III-Nitride FET and an enhancement mode group IV FET. In one exemplary implementation, the monolithically integrated half bridge includes a high side depletion mode III-Nitride FET having an enable switch coupled in the conduction path of the high side depletion mode III-Nitride FET.
1. An integrated half bridge circuit including a high side switch and a low side switch, said integrated half bridge circuit comprising:
a die including first and second depletion mode III-Nitride field-effect transistors (FETs) integrated thereon;
a group IV enhancement mode FET;
said group IV enhancement mode FET cascoded with said second depletion mode III-Nitride FET to provide a normally OFF composite cascoded switch as said low side switch;
a group IV enhancement mode insulated gate bipolar transistor (IGBT) enable switch being in a conduction path of said high side switch, said group IV enhancement mode IGBT enable switch having an emitter coupled to a switch node of said integrated half bridge circuit and a collector coupled to a load;
said group IV enhancement mode IGBT enable switch being configured to prevent shorting across a high voltage rail and a low voltage rail.
2. The integrated half bridge circuit of claim 1 , wherein said first and second depletion mode III-Nitride FETs comprise respective first and second III-Nitride High Electron Mobility Transistors (HEMTs).
3. The integrated half bridge circuit of claim 1 , wherein said group IV enhancement mode FET is integrated with said second depletion mode III-Nitride FET.
4. The integrated half bridge circuit of claim 1 , wherein said group IV enhancement mode IGBT enable switch is integrated with said half bridge circuit.
5. The integrated half bridge circuit of claim 1 , wherein said integration is based on a single gallium nitride (GaN) epitaxy-on-silicon substrate die.