Managing generated trace data for a virtual machine

1. A processor comprising:

a tracing register to store a value indicative of whether tracing is enabled or disabled;

a tracing module to generate trace data while tracing is enabled;

a buffer to store the trace data;

logic to write a value to the tracing register indicating that tracing is enabled in response to a request from a virtual machine, the request associated with a first trace output page and a second trace output page;

a trace translation lookaside buffer (TTLB) to store a first trace output page translation of the first trace output page and a second trace output page translation of the second trace output page;

logic to determine that the second trace output page is not resident in a main memory;

logic to copy the trace data to the first trace output page in the main memory in response to a determination that the second trace output page is not resident in the main memory; and

logic to load the second trace output page into the main memory using the second trace output translation and copy the trace data from the first trace output page to the second trace output page.

2. The processor of claim 1 , wherein the processor further comprises logic to, in response to the determination that the second trace output page is not resident in the main memory, pause the virtual machine, write a value to the tracing register indicating that the tracing is disabled, and remove the trace data from the buffer.

3. The processor of claim 2 , wherein the processor further comprises logic to, in response to the determination that the second trace output page is not resident in the main memory:

load the second trace output page into the main memory;

write a value to the tracing register indicating that tracing is enabled; and

resume the virtual machine.

4. The processor of claim 1 , wherein the processor further comprises logic to:

determine that the first trace output page includes at least a threshold level of data; and

write packets to the first trace output page indicating an overflow condition in response to determining that the first trace output page includes at least the threshold level of data.

5. The processor of claim 4 , wherein the processor further comprises logic to:

load the second trace output page into the main memory;

write packets to at least one of the first trace output page or the second trace output page indicating that tracing is re-enabled; and

write a value to the tracing register indicating that tracing is enabled.

6. The processor of claim 4 , wherein the threshold level of data is half a size of the first trace output page.

7. The processor of claim 1 , wherein the request is further associated with a third trace output page and the TTLB is to store a third trace output page translation of the third trace output page.

8. A method comprising:

receiving, from a virtual machine, a request to enabling tracing, the request associated with one or more trace output pages;

enabling tracing in response to the request;

storing trace data generated by the tracing in an internal buffer;

determining that one of the one or more trace output pages is not resident in main memory;

in response to determining that the one of the one or more trace output page is not resident in main memory, copying the trace data to a temporary trace storage buffer (TTSB), pausing the virtual machine, disabling tracing, and removing the trace data from the internal buffer;

loading the one or more trace output pages not in memory into the memory; and

copying the trace data from the TTSB to the one or more trace output pages.

9. The method of claim 8 , further comprising copying the trace data to the temporary trace storage buffer (TTSB) prior to removing the trace data from the internal buffer.

10. The method of claim 9 , further comprising, in response to determining that the one of the one or more trace output pages is not resident in the main memory:

loading the one of the one or more trace output pages into the main memory;

copying the trace data from the TTSB to the one of the one or more trace output pages;

re-enabling tracing; and

resuming the virtual machine.

11. The method of claim 8 , wherein the one or more trace output pages comprises a first trace output page and a second trace output page, and wherein determining that the one of the one or more trace output pages is not resident in the main memory comprises determining that the second trace output page is not resident in the main memory, and further comprising:

copying the trace data to the first trace output page prior to removing the trace data from the internal buffer.

12. The method of claim 11 , further comprising:

loading the second trace output page into the main memory;

re-enabling tracing; and

resuming the virtual machine.

13. The method of claim 11 , further comprising:

determining that the first trace output page includes at least a threshold level of data; and

writing packets to the first trace output page indicating an overflow condition in response to determining that the first trace output page includes at least the threshold level of data.

14. The method of claim 13 , further comprising:

loading the second trace output page into the main memory;

writing packets to at least one of the first trace output page or the second trace output page indicating that tracing is re-enabled; and

re-enabling tracing.

15. A system comprising:

main memory; and

a processor coupled to the main memory, the processor comprising:

a tracing register to store a value indicative of whether tracing is enabled or disabled;

a tracing module to generate trace data while tracing is enabled;

a buffer to store the trace data;

logic to write a value to the tracing register indicating that tracing is enabled in response to a request from a virtual machine, the request associated with a trace output page;

logic to determine that the trace output page is not resident in the main memory;

logic to copy the trace data in the buffer to a temporary trace storage buffer (TTSB) in the main memory in response to a determination that the output page is not resident in the main memory; and

logic to load the trace output page into the memory and copy the trace data from the TTSB to the trace output page.

16. The system of claim 15 , wherein the TTSB is a dedicated block of memory of the main memory.

17. The system of claim 15 , wherein the TTSB is a storage device separate from the main memory.

18. The system of claim 15 , wherein a size of the TTSB is less than a size of the trace output page.

19. The system of claim 15 , wherein the processor further comprises logic to, in response to the determination that the trace output page is not resident in the main memory, pause the virtual machine, write a value to the tracing register indicating that the tracing is disabled, and remove the trace data from the buffer.

20. The system of claim 15 , wherein the processor further comprises logic to, in response to the determination that the trace output page is not resident in the main memory:

load the trace output page into the main memory;

write a value to the tracing register indicating that tracing is enabled; and

resume the virtual machine.