IP Library Granted Patent US 9,665,397
Granted Patent B2
US 9,665,397 · App. 14/331,741 · Granted May 30, 2017

Hardware task manager

Inventors: W. James Scheuermann (Saratoga, CA); Eugene B. Hogenauer (San Carlos, CA)
Assignee: Cornami, Inc.
G06F9/4881G06F9/52G06F15/17331
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Quick Facts
Patent No.
US 9,665,397
App. No.
14/331,741
Granted
May 30, 2017
Kind
B2
Abstract

A hardware task manager for an adaptive computing system. The adaptive computing system includes a plurality of computing nodes including an execution unit configured to execute tasks. An interconnection network is operatively coupled to the plurality of computing nodes to provide interconnections among the plurality of computing nodes. The hardware task manager manages execution of the tasks by the execution unit.

Claims (28)

1. An integrated circuit comprising:

a plurality of computing nodes, at least one of the plurality computing nodes comprising an execution unit configured to execute tasks;

an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network configured to provide interconnections among the plurality of computing nodes; and

a hardware task manager in at least one of the plurality of computing nodes, the hardware task manager managing execution of tasks by the execution unit.

2. The integrated circuit of claim 1 , wherein the plurality of computing nodes comprise a plurality of heterogeneous computing nodes.

3. The integrated circuit of claim 1 , wherein the hardware task manager is configured to process the tasks in a task list.

4. The integrated circuit of claim 1 , wherein the hardware task manager is configured to maintain a state information table configured to provide the state of each task.

5. The integrated circuit of claim 1 , wherein the hardware task manager is configured to provide a ports count for a created task to indicate the availability of input ports and output ports to the created task.

6. The integrated circuit of claim 5 , wherein the availability is based on a predetermined amount of available data.

7. The integrated circuit of claim 1 , wherein the at least one computing node further comprises a node wrapper, the node wrapper interfacing the execution unit to the interconnection network.

8. An integrated circuit comprising:

a plurality of computing nodes, at least one computing node comprising an execution unit configured to execute tasks;

an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network configured to provide interconnections among the plurality of computing nodes;

a hardware task manager in at least one of the plurality of computing nodes; and

a ready-to-run queue in communication with the hardware task manager and configured to identify tasks that are ready to be executed by the execution unit.

9. The integrated circuit of claim 8 , wherein a task is identified as one of a plurality of states, the plurality of states selected from the group consisting of:

a suspend state identifying tasks created by a control node;

an idle state identifying tasks that are not ready for execution;

a ready state identifying tasks that are ready for execution; and

a run state identifying tasks that are being executed by the execution unit.

10. The integrated circuit of claim 8 , wherein a task is added to the ready-to-run queue when a task is identified as the ready state by the hardware task manager.

11. The integrated circuit of claim 8 , wherein the hardware task manager is configured to communicate with the execution unit to execute a task when the execution unit is idle and the task is the next task in the ready-to-run queue.

12. The integrated circuit of claim 8 , wherein the hardware task manager is further configured to determine a status of at least one buffer associated with a task and identify a task as ready to run based on the status of the at least one buffer.

13. The integrated circuit of claim 12 , wherein the at least one buffer comprises at least one input buffer and at least one output buffer.

14. The integrated circuit of claim 8 , wherein the hardware task manager is configured to identify the task as ready to run when the at least one input buffer and the at least one output buffer associated with the task are available.

15. The integrated circuit of claim 14 , wherein the hardware task manager is configured to determine the status of the at least one buffer using a buffer counter.

16. The integrated circuit of claim 15 , wherein the buffer counter is changed when a unit of data is placed into at least one buffer and when a unit of data is removed from the at least one buffer.

17. The integrated circuit of claim 8 , wherein each task is associated with a task identifier, and wherein the ready-to-run queue is configured to identify tasks in the ready-to-run queue with the task identifier.

Assignments (6)
CHANGE OF NAME Recorded Dec 9, 2016
From: SVIRAL, INC.
To: CORNAMI, INC.
Reel/Frame 040871/0147 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUS OMISSION OF THE SECOND INVENTOR PREVIOUSLY RECORDED ON REEL 038835 FRAME 0096. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 14, 2016
From: SCHEUERMANN, W. JAMES; HOGENAUER, EUGENE B.
To: QUICKSILVER TECHNOLOGY, INC.
Reel/Frame 038991/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2016
From: SCHEUERMANN, W. JAMES
To: QUICKSILVER TECHNOLOGY, INC.
Reel/Frame 038835/0096 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2016
From: QUICKSILVER TECHNOLOGY, INC.
To: TECHFARM VENTURES MANAGEMENT, LLC
Reel/Frame 038835/0284 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2016
From: TECHFARM VENTURES MANAGEMENT, LLC
To: QST HOLDINGS, LLC
Reel/Frame 038835/0707 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2016
From: QST HOLDINGS, LLC
To: SVIRAL, INC.
Reel/Frame 038835/0861 →
Continuity (5)
Continuation 13493216 · Jun 11, 2012
Continuation 12367690 · Feb 9, 2009
Continuation 10443501 · May 21, 2003
Provisional Application 60391874 · Jun 25, 2002
Related Publication 20140331231A1 · Nov 6, 2014