Method and apparatus for adapting a variable impedance network
The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.
1. A variable matching network, comprising:
a plurality of variable capacitors on a single die, wherein the single die has a plurality of ports coupled to the plurality of variable capacitors; and
a switching system comprising a group of switches, wherein the switching system is coupled with the plurality of variable capacitors to enable the variable matching network to be adjusted to a plurality of topologies according to switch positions of the group of switches,
wherein a first switch of the group of switches has a different conducting channel size than a second switch of the group of switches.
2. The variable matching network of claim 1 , wherein the switching system provides for a non-uniform quality (Q) factor, and wherein at least one topology of the plurality of topologies comprises a Tee topology.
3. The variable matching network of claim 1 , wherein the switching system provides for a non-uniform quality (Q) factor, and wherein at least one topology of the plurality of topologies comprises a Pi topology.
4. The variable matching network of claim 1 , wherein the switching system provides for a non-uniform quality (Q) factor, and wherein at least one topology of the plurality of topologies comprises an L topology.
5. The variable matching network of claim 1 , comprising first and second inductors, wherein the plurality of variable capacitors comprise first and second variable capacitors.
6. The variable matching network of claim 5 , wherein the first and second inductors are positioned off of the single die, and wherein the plurality of topologies comprise a Pi topology and an L topology.
7. The variable matching network of claim 1 , wherein at least one switch of the group of switches comprises a semiconductor switch, and wherein a scaling factor associated with the group of switches results in a non-uniform Q factor.
8. The variable matching network of claim 1 , wherein at least one switch of the group of switches comprises a micro-electro-mechanical systems (MEMS) switch, and wherein a scaling factor associated with the group of switches results in a non-uniform Q factor.
9. The variable matching network of claim 1 , wherein at least one variable capacitor of the plurality of variable capacitors is a voltage or current tunable capacitor comprising barium strontium titanate.
10. The variable matching network of claim 1 , wherein at least one variable capacitor of the plurality of variable capacitors comprises a plurality of fixed capacitors coupled to one or more switches.
11. The variable matching network of claim 1 , wherein at least two variable capacitors of the plurality of variable capacitors are in parallel.
12. The variable matching network of claim 1 , wherein at least two variable capacitors of the plurality of variable capacitors are in series.
13. A variable matching network comprising:
a plurality of variable capacitors on a single die, wherein the single die has a plurality of ports coupled to the plurality of variable capacitors; and
a switching system comprising a group of switches, wherein the switching system is coupled with the plurality of variable capacitors to enable the variable matching network to be adjusted to a plurality of topologies according to switch positions of the group of switches,
wherein at least one topology of the plurality of topologies is selected from a group of topologies consisting essentially of a Tee topology, a Pi topology, an L topology, or a combination thereof.
14. A variable matching network, comprising:
a plurality of variable capacitors on a single die, wherein the single die has a plurality of ports coupled to the plurality of variable capacitors; and
a switching system comprising a group of switches, wherein the switching system is coupled with the plurality of variable capacitors to enable the variable matching network to be adjusted to be one of a plurality of topologies according to switch positions of the group of switches,
wherein the one of the plurality of topologies is selected from a group of topologies consisting essentially of a Tee topology, a Pi topology, an L topology, or a combination thereof.
15. The variable matching network of claim 14 , wherein the one of the plurality of topologies is an L topology.
16. The variable matching network of claim 14 , comprising first and second inductors, wherein the plurality of variable capacitors comprise first and second variable capacitors.
17. The variable matching network of claim 16 , wherein the first and second inductors are positioned off of the single die.
18. The variable matching network of claim 14 , wherein at least one switch of the group of switches comprises one of a semiconductor switch or a micro-electro-mechanical systems (MEMS) switch.
19. The variable matching network of claim 14 , wherein at least one variable capacitor of the plurality of variable capacitors is a voltage or current tunable capacitor comprising barium strontium titanate.
20. A variable matching network, comprising:
a plurality of variable capacitors coupled to a plurality of ports; and
a switching system comprising a group of switches, wherein the switching system is coupled with the plurality of variable capacitors to enable the variable matching network to be adjusted to a plurality of topologies according to switch positions of the group of switches,
wherein the group of switches provides for a non-uniform Q factor based on at least one of a different conducting channel size of at least some switches or a parallel configuration of at least two switches,
wherein at least one topology of the plurality of topologies is selected from a group of topologies consisting essentially of a Pi topology, an L topology, or a combination thereof.