IP Library › Granted Patent US 9,299,774
Granted Patent B2
US 9,299,774 · App. 14/333,323 · Granted Mar 29, 2016

Device structure and methods of forming superjunction lateral power MOSFET with surrounding LDD

Inventors: Patrick M. Shea (Oviedo, FL); Samuel J. Anderson (Tempe, AZ); David N. Okada (Chandler, AZ)
Assignee: Great Wall Semiconductor Corporation
H01L29/0634H01L29/404H01L29/66659H01L29/66681H01L29/7823H01L29/7835
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Quick Facts
Patent No.
US 9,299,774
App. No.
14/333,323
Granted
Mar 29, 2016
Kind
B2
Abstract

A semiconductor device has a substrate and a gate formed over the substrate. An LDD region is formed in the substrate adjacent to the gate. A superjunction is formed in the LDD region while a portion of the LDD region remains between the superjunction and gate. A mask is formed over the substrate. A first region is doped with a first type of dopant using the mask. A stripe is doped with a second type of dopant using a portion of the mask. A drain contact region is formed in the substrate. The first region extends to the drain contact region. The first region and stripe are formed using chain implants. A source field plate and drain field plate are formed over the substrate. A trench is formed in the substrate. A source contact region is formed in the trench.

Claims (74)

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming a gate over the substrate;

forming a lightly doped drain (LDD) region in the substrate adjacent to the gate;

forming a first mask over the substrate including a portion of the first mask over the LDD region adjacent to the gate; and

forming a superjunction in the LDD region using the first mask.

2. The method of claim 1 , wherein forming the superjunction includes:

forming a first region doped with a first type of dopant using the first mask; and

forming a stripe doped with a second type of dopant using a portion of the first mask.

3. The method of claim 2 , further including:

forming a drain contact region in the substrate; and

forming the first region extending to the drain contact region.

4. The method of claim 2 , further including forming the first region and stripe using chain implants.

5. The method of claim 1 , further including:

forming a trench in the substrate; and

forming a source contact region in the trench.

6. The method of claim 1 , further including:

forming a source field plate over the substrate; and

forming a drain field plate over the substrate.

7. The method of claim 2 , further including forming the stripe using the portion of the first mask and a second mask.

8. A method of making a semiconductor device, comprising:

providing a substrate;

forming a gate over the substrate;

forming a lightly doped drain (LDD) region in the substrate adjacent to the gate;

forming a mask over the substrate; and

forming a superjunction in the LDD region using the mask.

9. The method of claim 8 , further including:

forming a drain contact region in the substrate; and

forming the superjunction while a first portion of the LDD region remains between the superjunction and gate and a second portion of the LDD region remains between the superjunction and drain contact region.

10. The method of claim 8 , wherein forming the superjunction includes:

forming a first region doped with a first type of dopant; and

forming a stripe doped with a second type of dopant and self-aligned to the first region.

11. The method of claim 10 , further including:

forming a drain contact region in the substrate; and

forming the first region extending to the drain contact region.

12. The method of claim 8 , further including forming the superjunction using chain implants.

13. The method of claim 8 , further including:

forming a trench in the substrate; and

forming a source contact region in the trench.

14. The method of claim 8 , further including:

forming a source field plate over the substrate; and

forming a drain field plate over the substrate.

15. A method of making a semiconductor device, comprising:

providing a substrate;

forming a lightly doped drain (LDD) region in the substrate;

forming a first mask over the substrate;

forming a first stripe doped with a first type of dopant in the LDD region using the first mask; and

forming a second stripe doped with a second type of dopant in the LDD region using the first mask, wherein the first stripe and second stripe form a superjunction.

16. The method of claim 15 , further including:

forming a drain contact region in the substrate; and

forming a portion of the superjunction extending to the drain contact region.

17. The method of claim 15 , further including forming the first stripe and second stripe using chain implants.

18. The method of claim 15 , further including:

forming a trench in the substrate; and

forming a source contact region in the trench.

19. The method of claim 15 , further including:

forming a source field plate over the substrate; and

forming a drain field plate over the substrate.

20. The method of claim 15 , further including forming the second stripe using the first mask and a second mask.

21. A method of making a semiconductor device, comprising:

providing a substrate;

forming a lightly doped drain (LDD) region in the substrate; and

forming a superjunction in the LDD region while a portion of the LDD region remains extending from a surface of the substrate at a first end of the superjunction to the surface of the substrate at a second end of the superjunction.

22. The method of claim 21 , wherein forming the superjunction includes:

forming a mask over the substrate;

forming a first region doped with a first type of dopant using the mask; and

forming a stripe doped with a second type of dopant using a portion of the mask.

23. The method of claim 21 , further including:

forming a drain contact region in the substrate; and

forming a portion of the superjunction extending to the drain contact region.

24. The method of claim 21 , further including forming the superjunction using chain implants.

25. The method of claim 21 , further including:

forming a trench in the substrate; and

forming a source contact region in the trench.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2014
From: SHEA, PATRICK M.; ANDERSON, SAMUEL J.; OKADA, DAVID N.
To: GREAT WALL SEMICONDUCTOR CORPORATION
Reel/Frame 033391/0539 →
Continuity (3)
Provisional Application 61856631 · Jul 19, 2013
Provisional Application 61857193 · Jul 22, 2013
Related Publication 20150021686A1 · Jan 22, 2015