Method and system for delta double sampling
An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples.
1. A method to attenuate circuit component offsets and mismatches, comprising:
precharging a pixel output to a first bias level, wherein the pixel includes a chemically-sensitive sensor and a select transistor that are a matched pair of transistors;
sampling a reference signal sample from the select transistor in the pixel;
canceling offset and mismatch signal artifacts from the reference sample to leave an offset and mismatch correction signal at a circuit node;
selecting an input signal from the chemically-sensitive sensor in the pixel, wherein the selected input signal is sampled;
adjusting the sampled input signal according to the offset and mismatch correction signal at the circuit node; and
converting the adjusted sampled input signal from an analog signal to a digital signal.