IP Library Granted Patent US 9,508,873
Granted Patent B2
US 9,508,873 · App. 14/339,915 · Granted Nov 29, 2016

Schottky diode and method of fabricating the same

Inventors: Dongwoo Suh (Daejeon, KR); Young Jun Kim (Daejeon, KR); Wei Lu (Ann Arbor, MI); Lin Chen (Ann Arbor, MI)
Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE; NATIONAL SCIENCE FOUNDATION
H01L29/872H01L29/068H01L29/0676H01L29/205H01L29/413H01L29/66212H01L29/2003
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Quick Facts
Patent No.
US 9,508,873
App. No.
14/339,915
Granted
Nov 29, 2016
Kind
B2
Abstract

Provided is a Schottky diode. The Schottky diode includes: a substrate; a core on the substrate; a metallic layer on the core; and a shell surrounding the core between the metallic layer and the substrate and adjusting a Fermi energy level of the core to form a Schottky junction between the core and the metallic layer.

Claims (35)

1. A Schottky diode comprising:

a substrate;

a core on the substrate;

a metallic layer on the core; and

a shell surrounding the core between the metallic layer and the substrate and adjusting a Fermi energy level of the core to form a Schottky junction between the core and the metallic layer,

wherein the core comprises a first semiconductor nanowire, and

wherein the shell comprises a second semiconductor having a different energy band gap from the first semiconductor nanowire and forming a heterojunction structure staggered with the first semiconductor nanowire.

2. The diode of claim 1 , wherein the first semiconductor nanowire extends vertically to the substrate.

3. The diode of claim of 1 , wherein each of the first semiconductor nanowire and the second semiconductor comprises an intrinsic semiconductor.

4. The diode of claim 1 , wherein the second semiconductor comprises an intrinsic silicon nanowire.

5. The diode of claim 1 , wherein the first semiconductor nanowire comprises an intrinsic germanium nanowire.

6. The diode of claim 1 , wherein the first semiconductor nanowire comprises an intrinsic germanium nanowire or an intrinsic silicon nanowire of which Fermi energy level is adjusted by the surface pinning effect or the surface Fermi energy pinning effect.

7. The diode of claim 1 , further comprising at least one insulating interlayer disposed between the metallic layer and the substrate to surround the shell.

8. The diode of claim 7 , wherein the insulating interlayer comprises a first insulating layer surrounding a sidewall of the shell and a second insulating layer surrounding a sidewall of the first insulating layer.

9. The diode of claim 1 , wherein the metallic layer extends from a top of the core and the shell to an external sidewall of the shell.

10. The diode of claim 1 , further comprising an interfacial layer disposed between the core and the metallic layer.

11. A Schottky diode comprising:

a substrate;

a core on the substrate;

a metallic layer on the core; and

a shell surrounding the core between the metallic layer and the substrate and adjusting a Fermi energy level of the core to form a Schottky junction between the core and the metallic layer,

wherein the metallic layer comprises:

a first metallic layer on the core and the shell; and

a second metallic layer on the first metallic layer,

wherein the first metallic layer forms the Schottky junction with respect to the core and the shell.

12. A method of fabricating a Schottky diode, the method comprising:

forming a core on a substrate;

forming a shell surrounding the core; and

forming a metallic layer on the shell and the core,

wherein the core forms a Schottky junction with the metallic layer by adjusting a Fermi energy level through the shell and the core is not doped with an impurity

wherein the core comprises a first semiconductor nanowire, and

wherein the shell comprises a second semiconductor having a different energy band gap from the first semiconductor nanowire and forming a heterojunction structure staggered with the first semiconductor nanowire.

13. The method of claim 12 , wherein the first semiconductor nanowire is formed through a vapor-liquid-solid (VLS) growth method.

14. The method of claim 12 , wherein the second semiconductor is formed through a chemical vapor deposition method or an atomic layer deposition method.

15. The method of claim 12 , further comprising forming an insulating interlayer surrounding the shell.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2017
From: SUH, DONGWOO; KIM, YOUNG JUN
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
Reel/Frame 041814/0281 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2017
From: LU, WEI; CHEN, LIN
To: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
Reel/Frame 042128/0727 →
CONFIRMATORY LICENSE Recorded Apr 24, 2015
From: UNIVERSITY OF MICHIGAN
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 035499/0221 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 24, 2014
From: SUH, DONGWOO; KIM, YOUNG JUN; LU, WEI; CHEN, LIN
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE; THE REGENTS OF THE UNIVERSITY OF MICHIGAN
Reel/Frame 033385/0036 →
Priority Claims (1)
KR 10-2013-0149225 · Dec 3, 2013 · national
Continuity (1)
Related Publication 20150155395A1 · Jun 4, 2015