Reconfigurable Automatic Test Circuit Techniques
A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device.
1 . A computer readable media including computer executable instructions which, when run on a computer, implement a method comprising:
providing, by a test processor, one or more adjustable timing signals to a programmable logic device;
implementing, by the programmable logic device, a sequence of states dependent on one or more input signals received from a device under test via a pin electronic circuit interface;
acquiring, by the programmable logic device, an output signal dependent on a current or previous sequence state in response to the one or more received input signals, wherein the output signal is indicative of a signal to be output by the pin electronics circuit interface to the device under test; and
adjusting, by the test processor, a timing used in a signal processing path through the programmable logic device used to acquire the output signal, wherein the timing is adjusted in response to at least one of the one or more adjustable timing signals.
2 . The computer readable media including the computer executable instructions which when run on the computer implement the method further comprising sampling by the test processor one or more signals provide by the pin electronic circuit in response to the one or more adjustable timing signals to acquire the one or more input signals.
3 . The computer readable media including the computer executable instructions which when run on the computer implement the method further comprising sampling by the test processor a signal provided by the programmable logic device in response to one of the adjustable timing signals to acquire the output signal.
4 . The computer readable media including the computer executable instructions which when run on the computer implement the method further comprising sampling a signal provided by the pin electronic circuit in response to one or more of the adjustable timing signals to acquire a sample of the input signal and to provide the sample to the programmable logic device.
5 . The computer readable media including the computer executable instructions which when run on the computer implement the method further comprising;
sampling by the test processor a signal provided by the pin electronics circuit in response to a first of the adjustable timing signals to acquire a sample of the input signal;
providing by the test processor the sample of the input signal to the programmable logic device in response to a second of the adjustable timing signals; and
adjusting by the test processor a timing relationship between the first of the adjustable timing signals and the second of the adjustable timing signals.
6 . An apparatus comprising:
a means for providing one or more timing signals;
a means for providing a sequence of states dependent on one or more input signals;
a means for providing an output signal dependent on a current or previous state in response to the one or more input signals; and
a means for adjusting a timing signal used in a signal processing path to provide the output signal in dependence on the one or more input signals.
7 . The apparatus of claim 6 , further comprising a means for sampling one or more signals in response to the one or more adjustable timing signals to acquire the one or more input signals or a signal in response to one of the adjustable timing signals to acquire the output signal.
8 . The apparatus of claim 6 , further comprising a means for sampling a signal in response to one or more of the adjustable timing signals to acquire a sample of the input signal and to provide the sample.
9 . The apparatus of claim 8 , further comprising a means to buffer a plurality of samples of the signal prior to forwarding the sample.
10 . The apparatus of claim 6 , further comprising:
a means for sampling a signal in response to a first of the adjustable timing signals to acquire a sample of the input signal;
a means for providing the sample of the input signal in response to a second of the adjustable timing signals; and
a means for adjusting a timing relationship between the first of the adjustable timing signals and the second of the adjustable timing signals.
11 . The apparatus of claim 6 , further comprising a means for sampling a data-out signal in response to one or more of the adjustable timing signals to acquire a sample of the data-out signal.
12 . The apparatus of claim 11 , further comprising a means to buffer a plurality of samples of the data-out signal prior to forwarding the samples of the data-out signal as the output signal.