IP Library Granted Patent US 10,343,899
Granted Patent B2
US 10,343,899 · App. 14/346,804 · Granted Jul 9, 2019

Method for wafer-level manufacturing of objects and corresponding semi-finished products

Inventors: Peter Riel (Bäch, CH); Hartmut Rudmann (Jona, CH); Markus Rossi (Jona, CH)
Assignee: ams Sensors Singapore Pte. Ltd.
B81B7/04B81C1/00904H01L27/14618H01L27/14685H01L27/14696H01L2924/0002Y10T29/49002Y10T428/18
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Quick Facts
Patent No.
US 10,343,899
App. No.
14/346,804
Granted
Jul 9, 2019
Kind
B2
Abstract

The method for manufacturing an object comprises the steps of (a) providing a wafer comprising a multitude of semi-finished objects; (b) separating said wafer into parts referred to as sub-wafers, at least one of said sub-wafers comprising a plurality of said semi-finished objects; (c) processing at least a portion of said plurality of semi-finished objects by subjecting said at least one sub-wafer to at least one processing step; and preferably also the step of (d) separating said at least one sub-wafer into a plurality of parts.

Claims (45)

1. A method for manufacturing an object, the method comprising the steps of:

(a) providing a wafer comprising semi-finished objects;

(b) separating said wafer into sub-wafers, at least one of said sub-wafers comprising a plurality of said semi-finished objects;

(c) processing at least a portion of said plurality of semi-finished objects by subjecting said at least one of said sub-wafers to at least one processing step, wherein said at least one processing step is applied to a separation face of said sub-wafer originating from step (b).

2. The method according to claim 1 , wherein said portion comprises at least two of said plurality of semi-finished objects.

3. The method according to claim 1 , wherein said portion comprises at least half of said plurality of semi-finished objects.

4. A method for manufacturing an object, the method comprising the steps of:

(a) providing a wafer comprising semi-finished objects;

(b) separating said wafer into sub-wafers, at least one of said sub-wafers comprising a plurality of said semi-finished objects;

(c) processing at least a portion of said plurality of semi-finished objects by subjecting said at least one of said sub-wafers to at least one processing step, wherein said at least one processing step comprises creating a slanted side wall of said sub-wafer slanted with respect to a lateral plane, wherein creating said slanted side wall is accomplished by removing material from said sub-wafer.

5. The method according to claim 4 , wherein step (c) is carried out while said plurality of said semi-finished objects is comprised in said sub-wafer.

6. The method according to claim 4 , wherein in step (c),

all the semi-finished objects of said portion of said plurality of semi-finished objects are simultaneously processed; or

the semi-finished objects of said portion of said plurality of semi-finished objects are subsequently processed.

7. The method according to claim 4 , wherein in step (c), each of said semi-finished objects of said at least one sub-wafer is processed by subjecting said at least one sub-wafer to at least one processing step.

8. The method according to claim 4 , wherein each of at least two of said sub-wafers comprises a respective plurality of said semi-finished objects, wherein the method comprises carrying out for each respective one of said at least two sub-wafers, the step of

(c′) processing at least a portion of the respective plurality of semi-finished objects of the respective sub-wafer by subjecting the respective sub-wafer to said at least one processing step.

9. The method according to claim 4 , wherein in said at least one sub-wafer, said plurality of said semi-finished objects forms a repetitive one-dimensional arrangement of said semi-finished objects.

10. The method according to claim 4 , wherein in said at least one sub-wafer, said plurality of said semi-finished objects is arranged along one or two straight lines.

11. The method according to claim 4 , wherein said at least one processing step comprises at least one of the group consisting of

a replication step;

a mechanical processing step;

a polishing step;

a grinding step;

a cutting step;

a chemical processing step;

a lithographic step;

a coating step; and

an etching step.

12. The method according to claim 4 , wherein said object is at least one of the group consisting of:

an optical element;

an optical device;

a substrate comprising at least one slanted face;

an optical sub-assembly comprising a substrate on which a light emitter is mounted, wherein said substrate on which a light emitter is mounted has at least one slanted face and/or wherein said light emitter is an edge-emitting light emitter and/or a laser;

an opto-electronic module;

an optical system;

a light-guiding device;

a micro-mechanical element;

a micro-electro-mechanical element;

a micro-electro-mechanical system.

13. The method according to claim 4 , wherein said wafer is at least partially made of a transparent polymer or of a glass.

14. The method according to claim 4 , comprising carrying out, after carrying out step (c), the step of

(d) separating said at least one sub-wafer into a plurality of parts, wherein each part comprises one of said processed semi-finished objects.

15. The method according to claim 4 , comprising carrying out, before carrying out step (b), the step of

(e) manufacturing said wafer.

Assignments (3)
CHANGE OF NAME Recorded Nov 3, 2025
From: AMS SENSORS SINGAPORE PTE. LTD.
To: AMS-OSRAM ASIA PACIFIC PTE. LTD.
Reel/Frame 073476/0659 →
CHANGE OF NAME Recorded Feb 8, 2019
From: HEPTAGON MICRO OPTICS PTE. LTD.
To: AMS SENSORS SINGAPORE PTE. LTD.
Reel/Frame 049222/0062 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2014
From: RIEL, PETER; RUDMANN, HARTMUT; ROSSI, MARKUS
To: HEPTAGON MICRO OPTICS PTE. LTD.
Reel/Frame 032840/0010 →
Continuity (2)
Provisional Application 61544005 · Oct 6, 2011
Related Publication 20140295122A1 · Oct 2, 2014