Array substrate, method for fabricating the same and display device
View Patent ↗An array substrate, a method for fabricating the same and a display device as provided relate to the field of display technologies and can overcome the disadvantage of the gate-source capacitance being inconstant and prevent screen flicker, thereby improving the display effect of the display device. The array substrate comprises a plurality of pixel units ( 31 ) arranged into an array and a gate line ( 32 ) and a data line ( 33 ) disposed as intersecting each other and corresponding to each of the pixel units ( 31 ), each of the pixel units comprising a TFT region ( 311 ) and a pixel electrode region ( 312 ), the TFT region ( 311 ) comprises at least two TFTs ( 34, 35 ); a source electrode ( 341, 351 ) of each of the TFTs is electrically connected to the data line ( 33 ), a gate electrode ( 342, 352 ) of each of the TFTs is electrically connected to the gate line ( 32 ), a drain electrode ( 343, 353 ) of each of the TFTs is electrically connected to a pixel electrode ( 312 ).
1. An array substrate, comprising a plurality of pixel units arranged as an array and a gate line and a data line disposed as intersecting each other and corresponding to each of the pixel units, each of the pixel units comprising a TFT region and a pixel electrode region, wherein the TFT region comprises at least two TFTs;
a source electrode of each of the TFTs is electrically connected to the data line, a gate electrode of each of the TFTs is electrically connected to the gate line, a drain electrode of each of the TFTs is electrically connected to the pixel electrode,
the data line is disposed in a periphery of the pixel unit, and the TFT region is located at one side of the data line, wherein the at least two TFTs all have a U-shaped TFT configuration, the source electrodes of the at least two TFTs are disposed as U shapes with openings opposite to each other, the drain electrodes of the at least two TFTs are correspondingly disposed in U-shaped recesses of the source electrodes of the at least two TFTs.
2. The array substrate of claim 1 , wherein the TFT region comprises two TFTs disposed opposed to each other.
3. The array substrate of claim 2 , wherein the two TFTs are of a same size.
4. The array substrate of claim 1 , wherein source electrodes of the at least two TFTs are an integral structure, drain electrodes of the at least two TFTs are an integral structure.
5. A display device comprising the array substrate of claim 1 .
6. A method for fabricating an array substrate, comprising:
forming a gate line and a gate electrode layer on a transparent substrate, the gate electrode layer comprising at least two gate electrodes configured for at least two TFTs, the at least two gate electrodes are all electrically connected to the gate line;
sequentially forming a semiconductor active layer and a gate protection layer on a surface of each gate electrode;
forming a data line, a pixel electrode and a source/drain electrode layer on the substrate having the semiconductor active layer and the gate protection layer formed thereon, wherein, the data line and the gate line are disposed as intersecting each other and corresponding to a pixel unit, the source/drain electrode layer comprises at least two source electrodes and at least two drain electrodes configured for at least two TFTs, the at least two source electrodes are all electrically connected to the data line, the at least two drain electrodes are all electrically connected to the pixel electrode, the data line is disposed in a periphery of the pixel unit, and the at least two TFTs are located at a same one side of the data line,
wherein the at least two TFTs all have a U-shaped TFT configuration, the source electrodes of the at least two TFTs are disposed as U shapes with openings opposite to each other, the drain electrodes of the at least two TFTs are correspondingly disposed in U-shaped recesses of the source electrodes of the at least two TFTs.
7. The method of claim 6 , wherein the gate electrode layer comprises two gate electrodes respectively configured for a first TFT and a second TFT disposed as opposed to each other.
8. The method of claim 7 , wherein a size of the first TFT is equal to that of the second TFT.
9. The method of claim 7 , wherein a source electrode of the first TFT and a source electrode of the second TFT are an integral structure, a drain electrode of the first TFT and a drain electrode of the second TFT are an integral structure.
10. The method of claim 9 , wherein the source electrode of the first TFT and the source electrode of the second TFT are formed of a same metal layer through a single patterning process, the drain electrode of the first TFT and the drain electrode of the second TFT are formed of a same metal layer through a single patterning process.
11. The method of claim 8 , wherein a source electrode of the first TFT and a source electrode of the second TFT are an integral structure, a drain electrode of the first TFT and a drain electrode of the second TFT are an integral structure.