Group III nitride high electron mobility transistor (HEMT) device
A group III nitride high electron mobility transistor (HEMT) device comprises a source electrode ( 112 ), a drain electrode ( 111 ), a main gate ( 116 ), a top gate ( 118 ), an insulating dielectric layer ( 117 ) and a heterostructure, wherein the source electrode ( 112 ) and the drain electrode ( 111 ) are electrically connected via two-dimensional electron gas (2DEG) formed in the heterostructure; the heterostructure comprises a first semiconductor ( 113 ) and a second semiconductor ( 114 ); the first semiconductor ( 113 ) is disposed between the source electrode ( 112 ) and drain electrode ( 111 ); the second semiconductor ( 114 ) is formed on the surface of the first semiconductor ( 113 ) and is provided with a band gap wider than the first semiconductor ( 113 ); the main gate ( 116 ) is disposed at the side of the surface of the second semiconductor ( 114 ) adjacent to the source electrode ( 112 ), and is in Schottky contact with the second semiconductor ( 114 ); the dielectric layer ( 117 ) is disposed on the surfaces of the second semiconductor ( 114 ) and the main gate ( 116 ) and between the source electrode ( 112 ) and the drain electrode ( 111 ); the top gate ( 118 ) is formed on the surface of the dielectric layer ( 117 ), at least one side edge of the top gate extends towards the direction of the source electrode ( 112 ) or the drain electrode ( 111 ), and the orthographic projection of the top gate overlaps with the two side edges of the main gate ( 116 ). When the HEMT device is at work, the main gate ( 116 ) and the top gate ( 118 ) are respectively controlled by a control signal. The device can effectively inhibit the “current collapse effect”.
1. A group III nitride high electron mobility transistor (HEMT) device, comprising: a source electrode, a drain electrode and a heterostructure, wherein the source electrode and the drain electrode are electrically connected via two-dimensional electron gas (2DEG) formed in the heterostructure; the heterostructure comprises a first semiconductor and a second semiconductor; the first semiconductor is disposed between the source electrode and drain electrode; the second semiconductor is formed on the surface of the first semiconductor and is provided with a band gap wider than the first semiconductor; the high electron mobility transistor (HEMT) device also comprises a main gate, a top gate and an insulating dielectric layer;
the main gate is disposed at the side of the surface of the second semiconductor adjacent to the source electrode, and is in Schottky contact with the second semiconductor;
the dielectric layer is disposed on the surfaces of the second semiconductor and the main gate is arranged between the source electrode and the drain electrode;
the top gate is formed on the surface of the dielectric layer, at least one side edge of the top gate extends towards the direction of source electrode or the drain electrode, and the orthographic projection of the top gate overlaps with the two side edges of the main gate;
when the HEMT device is at work, the main gate and the top gate are respectively controlled by a control signal.
2. The group III nitride high electron mobility transistor (HEMT) device according to claim 1 ,
characterized in that an insulating dielectric layer comprises a first dielectric layer and a second dielectric layer,
wherein the first dielectric layer is formed on the surface of the second dielectric layer;
the second dielectric layer is formed on the surface of the first dielectric layer and the main gate;
the main gate is disposed at the side of the surface of the first dielectric layer and is adjacent to the source electrode, and forms a metal-insulator-semiconductor structure with the first dielectric layer and the second semiconductor;
the top gate is formed on the surface of the dielectric layer, at least one side edge of the top gate extends towards the direction of the source electrode or the drain electrode, and the orthographic projection of the top gate overlaps with the two side edges of the main gate.
3. The group III nitride high electron mobility transistor (HEMT) device according to claim 1 or 2 , characterized in that a plasma processing region is formed inside the local region of the second semiconductor under the main gate.
4. The group III nitride high electron mobility transistor (HEMT) device according to claim 3 , characterized in that the plasma processing region is a fixed negative charge region formed by performing fluorine plasma treatment on the local region in the second semiconductor.
5. The group III nitride high electron mobility transistor (HEMT) device according to claim 1 or 2 , characterized in that the source electrode and the drain electrode are respectively connected to the low potential and high potential of a power supply.
6. The group III nitride high electron mobility transistor (HEMT) device according to claim 1 or 2 , characterized in that the first semiconductor and the second semiconductor are both group III nitride semiconductors.
7. The group III nitride high electron mobility transistor (HEMT) device according to claim 1 or 2 , characterized in that the two side edges of the top gate respectively extend towards the directions of the source electrode and the drain electrode.
8. The group III nitride high electron mobility transistor (HEMT) device according to claim 1 or 2 , characterized in that only one side edge of the top gate extends towards the direction of a corresponding source electrode or drain electrode.
9. The group III nitride high electron mobility transistor (HEMT) device according to claim 1 , characterized in that when the HEMT device is in a turn-on state, the potential of a control signal of the top gate is higher than that of a control signal of the main gate.