IP Library › Granted Patent US 10,048,551
Granted Patent B2
US 10,048,551 · App. 14/370,996 · Granted Aug 14, 2018

Semiconductor device, display device, and semiconductor device manufacturing method

Inventors: Tetsuo Fujita (Osaka, JP); Yoshihito Hara (Osaka, JP); Yukinobu Nakata (Osaka, JP)
Assignee: SHARP KABUSHIKI KAISHA
G02F1/13458G02F1/1368G02F1/134336H01L27/124H01L27/127H01L27/1225H01L27/1259H01L33/42G02F2001/134372
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Quick Facts
Patent No.
US 10,048,551
App. No.
14/370,996
Granted
Aug 14, 2018
Kind
B2
Abstract

A semiconductor device includes a thin-film transistor ( 101 ), a terminal portion ( 102 ), an interlevel insulating layer ( 14 ) including a first insulating layer ( 12 ) which contacts with the surface of a drain electrode ( 11 d ), and a first transparent conductive layer ( 15 ), a first dielectric layer ( 17 ) and a second transparent conductive layer ( 19 a ) formed on the interlevel insulating layer ( 14 ). The terminal portion ( 102 ) includes a lower conductive layer ( 3 t ), a second semiconductor layer ( 7 t ) arranged on a gate insulating layer ( 5 ), and lower and upper transparent connecting layers ( 15 t, 19 t ). The gate insulating layer ( 5 ) and the second semiconductor layer ( 7 t ) have a contact hole (CH 2 ), and their side surfaces located on a side of the contact hole (CH 2 ) are aligned with each other. The lower transparent connecting layer ( 15 t ) contacts with the lower conductive layer ( 3 t ) in the contact hole (CH 2 ). And the upper transparent connecting layer ( 19 t ) contacts with the lower transparent connecting layer ( 15 t ) at the bottom and on the sidewall of the contact hole (CH 2 ).

Claims (46)

1. A semiconductor device, comprising:

a substrate and a thin-film transistor, a gate line layer, a source line layer, and a terminal portion on the substrate, the gate line layer including a gate line, a gate electrode of the thin-film transistor, and a lower conductive layer of the terminal portion, the source line layer including a source line and source and drain electrodes of the thin-film transistor, the thin-film transistor including the gate electrode, a gate insulating layer on the gate electrode, a first semiconductor layer on the gate insulating layer including an oxide semiconductor, a protective layer which covers at least a channel region of the first semiconductor layer, the source electrode, and the drain electrode, wherein

the semiconductor device further includes:

an interlevel insulating layer on the source and the drain electrodes including a first insulating layer that contacts with at least a surface of the drain electrode;

a first transparent conductive layer on the interlevel insulating layer;

a first dielectric layer on the first transparent conductive layer; and

a second transparent conductive layer on the first dielectric layer overlapping with at least a portion of the first transparent conductive layer with the first dielectric layer between them,

the terminal portion includes:

the lower conductive layer;

the gate insulating layer extended onto the lower conductive layer;

a second semiconductor layer on the gate insulating layer and formed out of the same semiconductor film as the first semiconductor layer;

a lower transparent connecting layer formed out of the same conductive film as the first transparent conductive layer;

an upper transparent connecting layer on the lower transparent connecting layer and formed out of the same conductive film as the second transparent conductive layer, and

a second dielectric layer between the upper transparent connecting layer and the lower transparent connecting layer,

the gate insulating layer and the second semiconductor layer include a contact hole, and side surfaces of the gate insulating layer and the second semiconductor layer on a side of the contact hole are aligned with each other,

the lower transparent connecting layer is inside the contact hole and on the second semiconductor layer and contacts with the lower conductive layer in the contact hole,

the upper transparent connecting layer contacts with the lower transparent connecting layer at a bottom and on a sidewall of the contact hole,

the second dielectric layer covers a side surface of the lower transparent connecting layer and a side surface of the second semiconductor layer opposite to the contact hole, and contacts with an upper surface of the gate insulating layer, and

the upper transparent connecting layer covers an entire upper surface of the second dielectric layer and a side surface of the second dielectric layer opposite to the contact hole.

2. The semiconductor device of claim 1 , wherein the side surface of the lower transparent connecting layer is aligned with the side surface of the second semiconductor layer on an opposite side of the contact hole.

3. A display device comprising:

the semiconductor device of claim 1 ;

a counter substrate arranged so as to face the semiconductor device; and

a liquid crystal layer interposed between the counter substrate and the semiconductor device,

wherein the display device includes a plurality of pixels arranged in a matrix pattern, and

the second transparent conductive layer is divided into multiple portions which are allocated to the respective pixels and which function as pixel electrodes.

4. The display device of claim 3 , wherein the second transparent conductive layer has a plurality of slit holes in each said pixel, and

the first transparent conductive layer is located at least under the plurality of holes and functions as a common electrode.

5. The semiconductor device of claim 1 , wherein the oxide semiconductor includes an In—Ga—Zn—O-based semiconductor.

6. A semiconductor device, comprising:

a substrate; and

a terminal portion on the substrate, wherein

the terminal portion includes:

a lower conductive layer on the substrate;

an insulating layer covering the lower conductive layer;

a semiconductor layer on the insulating layer and includes an oxide semiconductor;

a lower transparent connecting layer;

an upper transparent connecting layer on the lower transparent connecting layer;

a dielectric layer between the upper transparent connecting layer and the lower transparent connecting layer,

the insulating layer and the semiconductor layer include a contact hole,

respective side surfaces of the insulating layer and the semiconductor layer on a side of the contact hole are aligned with each other,

the lower transparent connecting layer is inside the contact hole and on the semiconductor layer and contacts with the lower conductive layer inside the contact hole,

the upper transparent connecting layer contacts with the lower transparent connecting layer at a bottom and on a sidewall of the contact hole,

the dielectric layer covers a side surface of the lower transparent connecting layer and a side surface of the semiconductor layer opposite to the contact hole, and contacts with an upper surface of the insulating layer, and

the upper transparent connecting layer covers an entire upper surface of the dielectric layer, a side surface of the dielectric layer opposite to the contact hole, and directly contacts the insulating layer.

7. The semiconductor device of claim 6 , wherein the oxide semiconductor includes an In—Ga—Zn—O-based semiconductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2014
From: FUJITA, TETSUO; HARA, YOSHIHITO; NAKATA, YUKINOBU
To: SHARP KABUSHIKI KAISHA
Reel/Frame 033259/0843 →
Priority Claims (1)
JP 2012-003464 · Jan 11, 2012 · national
Continuity (1)
Related Publication 20140347590A1 · Nov 27, 2014