SiC bipolar junction transistor with reduced carrier lifetime in collector and a defect termination layer
A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT ( 100 ) are provided. The SiC BJT comprises an emitter region ( 150 ), a base region ( 140 ) and a collector region ( 120 ). The collector region is arranged on a substrate ( 110 ) having an off-axis orientation of about 8 degrees or lower. A defect termination layer (DTL, 130 ) for terminating dislocations originating from the substrate is arranged between the substrate and the collector region. The collector region includes a zone ( 125 ) in which the life time of the minority charge carriers is shorter than in the base region. The present invention is advantageous in terms of improved stability of the SiC BJTs.
1. An apparatus, comprising:
an emitter region, a base region, and a collector region included in a silicon carbide (SiC) bipolar junction transistor, the collector region being arranged on a SiC substrate having an off-axis orientation of 8 degrees or lower;
a defect termination layer, DTL, for terminating dislocations originating from the substrate, the DTL being arranged between the substrate and the collector region; and
a zone in which the minority charge carriers have lifetimes shorter than in the base region such that the zone is configured to prevent access of minority charge carriers from the collector region to the DTL, the zone having at least a portion disposed between the base region and the DTL.
2. The apparatus of claim 1 , wherein the zone extends laterally at least under a metallurgical junction formed by the base region and the emitter region.
3. The apparatus of claim 1 , wherein the zone covers at least 10 percent of a volume of the collector region.
4. The apparatus of claim 1 , wherein the zone extends vertically towards the DTL, starting at a distance of 1-4 μm from a metallurgical junction formed by the base region and the collector region.
5. The apparatus of claim 1 , wherein the zone is arranged in a lower part of the collector region.
6. The apparatus of claim 1 , wherein the zone extends vertically through the whole collector region.
7. The apparatus of claim 1 , wherein minority charge carriers in the DTL have lifetimes shorter than in the base region.
8. The apparatus of claim 1 , wherein the minority charge carriers have lifetimes in the zone less than 200 nanoseconds.
9. The apparatus of claim 1 , wherein the minority charge carrier lifetime in the zone is two times less than in the base region.
10. The apparatus of claim 1 , wherein the zone includes at least one of a damaged crystallographic structure, an ion-bombarded zone, or an electron-irradiated zone.
11. The apparatus of claim 1 , wherein at least one of the base region or the emitter region have a lower concentration of carbon vacancies than the collector region.
12. The apparatus of claim 1 , wherein the substrate has an off-axis orientation of 2-4 degrees.
13. The apparatus of claim 1 , wherein the DTL has a thickness in a range of 5-30 micrometers.
14. The apparatus of claim 1 , wherein the zone is disposed in the collector region.
15. The apparatus of claim 1 , wherein the zone extends into the DTL.
16. The apparatus of claim 1 , wherein the apparatus is a bipolar junction transistor (BJT).
17. The apparatus of claim 1 , wherein the zone is disposed in proximity to an interface between the collector region and the DTL.
18. A semiconductor device, comprising:
a first region disposed on a silicon carbide (SiC) substrate, the first region having a first conductivity type;
a second region disposed on the first region, the second region having a second conductivity type opposite to the first conductivity type;
a third region disposed on the second region and having the first conductivity type, the first region, the second region, and the third region being included in a SiC bipolar junction transistor;
a defect termination layer (DTL) disposed between the substrate and the first region for terminating dislocations originating from the substrate; and
a zone in which minority charge carriers have lifetimes shorter than in the second region such that the zone is configured to prevent access of minority charge carriers from the first region to the DTL, the zone having at least a portion disposed between the second region and the DTL.
19. The semiconductor device of claim 18 , wherein the zone extends laterally at least under a metallurgical junction formed by the second region and the third region.
20. The semiconductor device of claim 18 , wherein the zone covers at least 10 percent of a volume of the first region.
21. The semiconductor device of claim 18 , wherein the zone extends vertically towards the DTL, starting at a distance of 1-4 μm from a metallurgical junction formed by the second region and the first region.
22. The semiconductor device of claim 18 , wherein the zone is arranged in a lower part of the first region.
23. The semiconductor device of claim 18 , wherein the zone extends vertically through the whole first region.