Array substrate and a method for manufacturing the same
An array substrate is disclosed. The array substrate comprises a base substrate ( 4 ) and signal lines on the base substrate ( 4 ). The signal lines comprises a plurality of conductive layers ( 11, 12 ) in different layers, and the plurality of conductive layers ( 11, 12 ) are provided with insulation layers ( 21 ) therebetween, and are connected in parallel through one or more vias ( 3 ). Embodiments of the present disclosure further disclose a method for manufacturing the array substrate.
1. A method for manufacturing an array substrate, the array substrate comprising a base substrate and signal lines disposed on the base substrate, wherein the array substrate further comprise a plurality of conductive layers disposed in different layers, the plurality of conductive layers are provided with insulation layers therebetween and are connected in parallel with each other through one or more vias, wherein the method comprises:
forming a first conductive layer and a first insulation layer by deposition on a base substrate;
etching the first insulation layer to form a via passing through the first insulation layer;
forming a second conductive layer by deposition on the base substrate, wherein the second conductive layer is formed by deposition on the first insulation layer and in the via such that the first conductive layer and the second conductive layer are connected in parallel with each other through the via;
and wherein, after forming the first conductive layer and the first insulation layer by deposition on the base substrate, the method further comprises:
sequentially forming a third conductive layer and a second insulation layer by deposition on the first insulation layer;
forming the via comprises;
etching the second insulation layer, the third conductive layer and the first insulation layer to form the via passing through the second insulation layer, the third conductive layer and the first insulation layer;
forming the second conductive layer by deposition comprises:
forming the second conductive layer by deposition on the second insulation layer and in the via such that the first conductive layer, the third conductive layer and the second conductive layer are connected in parallel through the via;
wherein the signal lines are gate lines, the first conductive layer is a gate metal layer, the third conductive layer is a data line layer disposed in a gate line region, and the second conductive layer is a pixel electrode layer disposed in the gate line region; or
the signal lines are data lines, the first conductive layer is a gate metal layer disposed in a data line region, the third conductive layer is a data line layer disposed in a data line region, and the second conductive layer is a pixel electrode layer disposed in the data line region,
wherein at the overlapping position of projections of the gate lines and the data lines, each of the signal lines will only have one of the conductive layers, that is the gate layer will only remain as the gate line and the data line layer will only remain as the data line.
2. The method according to claim 1 , further comprising forming a semiconductor layer, which is connected to the signal lines so as to reduce resistance.