Method of fabricating a tunnel oxide layer and a tunnel oxide layer for a semiconductor device
View Patent ↗A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.
1. A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising:
fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and
fabricating at least one further oxide layer by a furnace oxidation process,
wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.
2. The method of claim 1 , wherein fabricating the first oxide layer results in the first oxide layer having a thickness in the range from 25 Å to 35 Å.
3. The method of claim 1 , wherein the duration of the in-situ-steam-generation process is in the range from 30 seconds to 45 seconds.
4. The method of claim 1 , wherein the duration of the in-situ-steam-generation process is in the range from 35 seconds to 40 seconds.
5. The method of claim 1 , wherein the temperature of the in-situ-steam-generation process is in the range from 900 degrees Celsius to 1000 degrees Celsius.
6. The method of claim 1 , wherein a second portion of the at least one further oxide layer is fabricated adjacent to the first oxide layer.
7. The method of claim 6 , wherein the thickness of the second portion of the at least one further oxide layer fabricated next to the first oxide layer is in the range from 25 Å to 35 Å.
8. The method of claim 1 , wherein the in-situ-steam-generation process uses an oxygen gas flow in the range from 8.18*10 −5 m 3 /s to 8.35*10 −5 m 3 /s per silicon wafer.
9. The method of claim 1 , wherein the in-situ-steam-generation process uses a hydrogen gas flow in the range from 0.0167*10 −5 m 3 /s to 0.167*10 −5 m 3 /s per silicon wafer.
10. The method of claim 1 , wherein the pressure applied during the in-situ-steam-generation process is in the range from 1200 Pa to 1333 Pa.
11. A method according to claim 1 , wherein a second portion of the at least one further oxide layer is fabricated on the substrate adjacent to the first oxide layer.
12. The method of claim 1 , wherein fabricating the at least one further oxide layer comprises fabricating first and second further oxide layers, each fabricated by a furnace oxidation process, wherein a first portion of the second further oxide layer is formed beneath the first oxide layer.
13. The method of claim 12 , wherein the combined thickness of the first oxide layer and first and second further oxide layers is in the range from 68 Å to 80 Å.
14. A method according to claim 12 , wherein a second portion of the second further oxide layer is formed beneath a second portion of the first further oxide layer fabricated adjacent to the first oxide layer, wherein during fabrication of the second portion of the second further oxide layer, reactive gases penetrate the second portion of the first further oxide layer and react with the silicon substrate to form the second portion of the second further oxide layer beneath the second portion of the first further oxide layer.
15. A method according to of claim 14 , wherein a third portion of the second further oxide layer is formed on the substrate adjacent to the second portion of the second further oxide layer.
16. The method of claim 12 , further comprising, after the fabrication of said first oxide layer and first further oxide layer and before the fabrication of said second further oxide layer:
covering at least a portion of the first oxide layer and a portion of the first further oxide layer with a mask;
wet cleaning to remove from the substrate the portion of the first oxide layer and/or first further oxide layer not covered by the mask; and
removing the mask.
17. The method of claim 1 , wherein said first, and at least one further oxide layers are formed without use of plasma nitridation.
18. The method of claim 1 , wherein the semiconductor memory device is a single poly floating gate erasable programmable read only memory.
19. The method of claim 1 , wherein the semiconductor memory device is a single poly floating gate electrically erasable programmable read-only memory.
20. A tunnel oxide layer for a semiconductor memory device manufactured by:
fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and
fabricating at least one further oxide layer by a furnace oxidation process,
wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.
21. A semiconductor device comprising a tunnel oxide layer manufactured by:
fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and
fabricating at least one further oxide layer by a furnace oxidation process,
wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.
22. A tunnel oxide layer for a semiconductor memory device comprising an in situ-steam generation (ISSG) oxide layer positioned on top of at least one furnace oxidation oxide layer, wherein the ISSG oxide layer and the at least one furnace oxidation oxide layer are stacked.