Reducing solder pad topology differences by planarization
View Patent ↗A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.
1. A method comprising:
providing an electronic device with a first surface and a second surface opposite the first surface;
providing a first solder pad at a first distance above the first surface and a second solder pad at second distance above the first surface, the first distance being different from the second distance;
providing a dielectric layer between the first solder pad and the second solder pad;
after the step of providing the dielectric layer, plating a first metal layer portion over the first solder pad above a height of the dielectric layer so that, immediately after the step of plating, the first metal layer portion extends above any insulating material;
after the step of providing the dielectric layer, plating a second metal layer portion, concurrently with plating the first metal layer portion, over the second solder pad above the height of the dielectric layer so that, immediately after the step of plating, the second metal layer portion extends above any insulating material;
planarizing the first metal layer portion and the second metal layer portion, so that the step of planarizing planarizes only the material forming the first metal layer portion and the second metal layer portion, resulting in the first metal layer and the second metal layer having a third and a fourth surface respectively, wherein the third surface and the fourth surface are in the same plane and still have a height above the height of the dielectric layer,
depositing a first solder layer over the first metal layer portion; and
depositing a second solder layer over the second metal layer portion, such that a top surface of the first solder layer is in the same plane as a top surface of the second solder layer.
2. The method of claim 1 :
wherein the plated first metal portion has a fifth surface connected to the first solder pad and a sixth surface opposite the fifth surface,
wherein the plated second metal portion has a seventh surface connected to the second solder pad and an eight surface opposite the seventh surface, and
wherein the dielectric layer is closer to the first surface than any point of the sixth and eight surfaces.
3. The method of claim 1 wherein the electronic device is a chip after singulation from a wafer.
4. The method of claim 3 further comprising:
positioning the chip with respect to a substrate having a third solder pad corresponding to the first solder pad and having a fourth solder pad corresponding to the second solder pad;
bonding the first solder layer to the third solder pad; and
bonding the second solder layer to the fourth solder pad.
5. The method of claim 4 wherein bonding the first solder layer to the third solder pad and bonding the second solder layer to the fourth solder pad are by solder reflow.
6. The method of claim 4 wherein bonding the first solder layer to the third solder pad and bonding the second solder layer to the fourth solder pad are by ultrasonic bonding.
7. The method of claim 1 :
wherein planarizing the first metal layer portion and the second metal layer portion comprises planarizing the first metal layer portion and the second metal layer portion to be higher than the dielectric portion.
8. The method of claim 1 wherein the electronic device is a chip after singulation from a wafer, and wherein the chip is a flip chip light emitting diode.
9. The method of claim 1 wherein the electronic device is a chip after singulation from a wafer, and wherein the chip is an integrated circuit.
10. The method of claim 1 wherein the plane is parallel to the first surface.
11. The method of claim 1 wherein the first surface of the electronic device forms a first plane, and wherein the plane of the top surface of the first solder layer and top surface of the second solder layer form a second plane that is not parallel to the first plane.