Sequential logic circuit and method of providing setup timing violation tolerance therefor
A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state, and a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby comprising a first logical state. The sequential logic circuit is arranged to operate in at least a first operating mode in which the data input of the first latch component and the data input of the second latch component are operably coupled to a first input of the sequential logic circuit, and in which the clock signals provided to the first and second latch components are such that a transition of the second latch component from a transparent state to a latched state is delayed relative to a corresponding transition of the first latch component from a transparent state to a latched state for a time period for receiving late data.
1. A sequential logic circuit comprising:
a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state; and
a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby comprising a first logical state;
wherein the sequential logic circuit is arranged to operate in at least a first operating mode in which the data input of the first latch component and the data input of the second latch component are operably coupled to a first input of the sequential logic circuit, and in which the clock signals provided to the first and second latch components are such that a transition of the second latch component from a transparent state to a latched state is delayed relative to a corresponding transition of the first latch component from a transparent state to a latched state for a time period for receiving late data.
2. The sequential logic circuit of claim 1 , wherein the same clock signal is provided to the first and second latch components.
3. The sequential logic circuit of claim 1 , wherein the sequential logic circuit further comprises a comparator component, the comparator component being arranged to, at least when the sequential logic circuit is operating in the first operating mode and during the time period for receiving late data:
receive at a first input thereof an indication of a latched logical state of the first latch component;
receive at a second input thereof an indication of a logical state of the first input of the sequential logic circuit; and
output from an output thereof an indication of whether the logical state of the first input of the sequential logic circuit differs from the latched logical state of the first latch component.
4. The sequential logic circuit of claim 3 , wherein the second input of the comparator component is operably coupled to the second latch component and arranged to receive an indication of a current logical state of the second latch component.
5. The sequential logic circuit of claim 3 , wherein the comparator component comprises an eXclusive OR, XOR, gate.
6. The sequential logic circuit of claim 1 , wherein the sequential logic circuit is configurable to operate in at least one further mode of operation in which the data input of the first latch component is operably coupled to a second input of the sequential logic circuit.
7. The sequential logic circuit of claim 6 , wherein the sequential logic circuit comprises a first multiplexer component comprising:
a first data input operably coupled to the first input of the sequential logic circuit;
a second data input operably coupled to the second input of the sequential logic circuit;
an output operably coupled to the data input of the first latch component; and
a control input arranged to receive a control signal,
wherein the first multiplexer component is arranged to selectively output to the first latch component a logical state of one of the first input of the sequential logic circuit and the second input of the sequential logic circuit in accordance with the control signal received thereby.
8. The sequential logic circuit of claim 1 , wherein the sequential logic circuit is configurable to operate in at least one further mode of operation in which the data input of the second latch component is operably coupled to the output of the first latch component.
9. The sequential logic circuit of claim 8 , wherein the sequential logic circuit comprises a second multiplexer component comprising:
a first data input operably coupled to the first input of the sequential logic circuit;
a second data input operably coupled to the output of the first latch component;
an output operably coupled to the data input of the second latch component; and
a control input arranged to receive a control signal,
wherein the second multiplexer component is arranged to selectively output to the second latch component a logical state of one of the first input of the sequential logic circuit and the output of the first latch component in accordance with the control signal received thereby.
10. The sequential logic circuit of claim 1 , wherein the sequential logic circuit further comprises a third latch component comprising a data input/output operably coupled to the second latch component, and a clock input arranged to receive a clock signal; the third latch component being arranged to comprise:
a transparent state in which the third latch component receives an indication of a current logical state of the second latch component via the data input/output thereof, upon the clock signal received thereby comprising a first logical state; and
a latched state in which the third latch component outputs its current logical state to the second latch component via the data input/output thereof, upon the clock signal received thereby comprising a second logical state.
11. The sequential logic circuit of claim 10 , wherein the same clock signal is provided to the second and third latch components.
12. The sequential logic circuit of claim 1 implemented within an integrated circuit device comprising at least one die within a single integrated circuit package.
13. A digital synchronous system comprising at least one sequential logic circuit according to claim 1 .
14. A method of providing setup timing violation tolerance within a sequential logic circuit, the method comprising, upon receipt of an active clock edge at the sequential logic circuit:
sampling a logical state of a data input of the sequential logic circuit;
configuring a transparent path between the data input of the sequential logic circuit and a data output of the sequential logic circuit during a time period for receiving late data following receipt of the active clock edge, said timer period for receiving late data being less than a clock cycle period; and
latching the data output of the sequential logic circuit after expiry of the time period for receiving late data.
15. The method of claim 14 , wherein the time period for receiving late data comprises a period equal to half a clock cycle period.
16. The method of claim 15 , wherein the active clock edge comprises a transition of a logical state of a clock signal received by the sequential logic circuit from a first logical state to a second logical state, and the method comprises latching the data output of the sequential logic circuit upon a transition of a logical state of the clock signal from the second logical state to the first logical state.
17. The method of claim 14 , wherein the method further comprises:
comparing the sampled logical state of the data input of the sequential logic circuit with a logical state of the data input of the sequential logic circuit during the time period for receiving late data; and
outputting an indication of whether the logical state of the data input of the sequential logic circuit differs from the sampled logical state during the time period for receiving late data.