Clock for serial communication device
View Patent ↗Versatility and flexibility of integrated circuits can be accomplished by remote control via a serial interface, such as SPI. Read/write accesses to the SPI slave node can be achieved according to SPI protocol by the master node. Additionally, a state machine associated to the slave node SPI needs a local clock to exercise the control of the analog functions following a write access. The serial protocol defines a serial data word transfer to comprise a number of reserved clock cycles that are not assigned for communicating a data bit value of the data word. The slave device comprises a clock unit coupled to the serial clock line for providing a derived clock based on reserved clock cycles. The derived clock is used internally in the slave device to perform internal synchronous operations.
1. An electronic device comprising:
a serial interface circuit to communicate with a master device according to a serial protocol via a serial data line and a serial clock line, wherein the serial protocol defines:
a clock cycle comprising a clock pulse on the serial clock line and a serial data bit value on the serial data line to be communicated synchronously to said clock pulse; and
a serial data word transfer comprising a predetermined number of clock cycles to communicate a data word having data bit values and a further predetermined number of reserved clock cycles that are not assigned to communicate a data bit value of the data word; and
the device comprises:
a clock circuit, coupled to the serial clock line, and configured to provide a derived clock based on the clock pulses of the reserved clock cycles of the serial data word,; and
a control circuit configured to perform a logical operation based on the derived clock.
2. The device as claimed in claim 1 , wherein the serial protocol further defines the serial data word transfer as a write access to the device, in which the predetermined number of clock cycles is followed by the reserved clock cycles.
3. The device as claimed in claim 1 , wherein the control circuit is arranged to control an analog function based the derived clock by the data bit values of the transferred data word.
4. The device as claimed in claim 1 , wherein the serial protocol further defines the serial data word transfer as a read access from the device, in which the predetermined number of clock cycles is preceded by the reserved clock cycles.
5. The device as claimed in claim 4 , wherein the control circuit is arranged to retrieve a data result from an analog function based on the derived clock and to output the data result as the data bit values of the transferred data word.
6. The device as claimed in claim 1 , wherein the serial protocol defines:
a first serial data word transfer comprising a first predetermined number of clock cycles to communicate a data word having the number of data bit values; and
a second serial data word transfer comprising the predetermined number of clock cycles to communicate a data word having less data bit values than the number of data bit values, the remaining number of said predetermined number of clock cycles constituting the reserved clock cycles.
7. The device as claimed in claim 6 , wherein the predetermined number of clock cycles is eight and the remaining number constituting the reserved clock cycles is two.
8. The device as claimed in claim 6 , wherein the first predetermined number of clock cycles is 16, 24, or 32 and the remaining number constituting the reserved clock cycles is 2, 4, 6, or 8.
9. A master device comprising:
a serial interface circuit to communicate with a serial slave device according to a serial protocol via a serial data line and a serial clock line, wherein the serial protocol defines:
a clock cycle comprising a clock pulse on the serial clock line and a serial data bit value on the serial data line to be communicated synchronously to said clock pulse; and
a serial data word transfer comprising a predetermined number of clock cycles for communicating a data word having data bit values;
the serial interface circuit is configured to accommodate the serial data word transfer to comprise a further predetermined number of reserved clock cycles that are not assigned to communicate a data bit value of the data word; and
the slave device comprises:
a clock circuit arranged to be coupled to the serial clock line to provide a derived clock based on the clock pulses of the reserved clock cycles of the serial data word; and
a control circuit to perform a logical operation based on the derived clock.
10. The master device as claimed in claim 9 , wherein the serial protocol further defines the serial data word transfer as a write access to the device, in which the predetermined number of clock cycles is followed by the reserved clock cycles.
11. The master device as claimed in claim 9 , wherein the serial protocol further defines the serial data word transfer as a read access from the device, in which the predetermined number of clock cycles is preceded by the reserved clock cycles.
12. The master device as claimed in claim 11 , wherein the control circuit is arranged for inputting a data result from an analog function in the slave device based the derived clock.
13. The master device as claimed in claim 9 , wherein the serial protocol defines:
a first serial data word transfer comprising a first predetermined number of clock cycles for communicating a data word having a first predetermined number of data bit values; and
a second serial data word transfer comprising the first predetermined number of clock cycles for communicating a data word having less data bit values than the first predetermined number of data bit values, the remaining number of said first predetermined number of clock cycles constituting the reserved clock cycles.
14. The master device as claimed in claim 13 , wherein the first predetermined number is eight and the remaining number constituting the reserved clock cycles is two.
15. The master device as claimed in claim 13 , wherein the first predetermined number is 16, 24, or 32 and the remaining number constituting the reserved clock cycles is 2, 4, 6, or 8.
16. A method of communicating between a slave device and a master device according to a serial protocol via a serial data line and a serial clock line, the serial protocol defining a clock cycle comprising a clock pulse on the serial clock line and a serial data bit value on the serial data line to be communicated synchronously to said clock pulse, and a serial data word transfer comprising a predetermined number of clock cycles for communicating a data word having data bit values, the method comprising:
transferring, in the serial data word transfer according to the serial protocol, a further predetermined number of reserved clock cycles that are not assigned for communicating a data bit value of the data word; and
providing a derived clock based on the clock pulses of the reserved clock cycles of the serial data word, and performing a logical operation based on the derived clock.
17. The method as claimed in claim 16 , wherein the serial protocol further defines the serial data word transfer as a write access to the device, in which the predetermined number of clock cycles is followed by the reserved clock cycles.
18. The method as claimed in claim 16 , wherein the serial protocol defines:
a first serial data word transfer comprising a first predetermined number of clock cycles for communicating a data word having a first predetermined number of data bit values; and
a second serial data word transfer comprising the first predetermined number of clock cycles for communicating a data word having less data bit values than the first predetermined number of data bit values, the remaining number of said first predetermined number of clock cycles constituting the reserved clock cycles.
19. The method as claimed in claim 18 , wherein the first predetermined number is eight and the remaining number constituting the reserved clock cycles is two.
20. The method as claimed in claim 18 , wherein the first predetermined number is 16, 24, or 32 and the remaining number constituting the reserved clock cycles is 2, 4, 6, or 8.