Semiconductor ferroelectric storage transistor and method for manufacturing same
Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body ( 11 ) and a gate electrode conductor ( 4 ) are sequentially laminated in this order on a semiconductor base ( 10 ) that has a source region ( 12 ) and a drain region ( 13 ). The insulating body ( 11 ) is configured by laminating a first insulating body ( 1 ) and a second insulating body ( 2 ) in this order on the base ( 10 ), and the second insulating body ( 2 ) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.
1. A semiconductor ferroelectric memory transistor, comprising:
a semiconductor body which has a source region and a drain region on which an insulator and a gate electrode conductor are stacked in that order;
wherein the insulator includes a ferroelectric insulator comprising an oxide of strontium, calcium, bismuth, and tantalum, and
wherein the insulator is comprised of a first insulator, a second insulator, and a third insulator stacked on the body in that order, and wherein the second insulator is mainly comprised of the oxide of strontium, calcium, bismuth, and tantalum.
2. The semiconductor ferroelectric memory transistor according to claim 1 , wherein in the oxide of strontium, calcium, bismuth, and tantalum, a ratio of a calcium element to a strontium element is larger than 0 and not more than two-thirds.
3. The semiconductor ferroelectric memory transistor according to claim 1 , wherein the oxide of strontium, calcium, bismuth, and tantalum has a bismuth layered perovskite-type crystal structure.
4. The semiconductor ferroelectric memory transistor according to claim 1 , wherein the first insulator is an oxide of halfnium, an oxide of halfnium and aluminum, an oxide which includes halfnium, an oxide of strontium and titanium, a composite oxide of two or more of any of these, or an oxide layer stack of two or more of any of these.
5. The semiconductor ferroelectric memory transistor according to claim 1 , wherein the third insulator is an oxide of halfnium, an oxide of halfnium and aluminum, an oxide which includes halfnium, an oxide of strontium and titanium, a composite oxide of two or more of any of these, or an oxide layer stack of two or more of any of these.
6. The semiconductor ferroelectric memory transistor according to claim 1 or 5 , wherein the insulator has a film thickness of 250 nm or less.
7. The semiconductor ferroelectric memory transistor according to claim 1 or 5 , wherein the first or third insulator has a film thickness of 15 nm or less.
8. A method of producing a semiconductor ferroelectric memory transistor according to claim 1 ,
the method comprising:
cleaning a semiconductor body surface;
depositing an insulator;
forming a gate electrode conductor; and
providing a heat treatment;
wherein the semiconductor ferroelectric memory transistor includes the semiconductor body having a source region and a drain region on which the insulator including a ferroelectric insulator comprising an oxide of strontium, calcium, bismuth, and tantalum and a gate electrode conductor, all of which are stacked in that order.
9. The semiconductor ferroelectric memory transistor according to claim 2 , wherein the insulator has a film thickness of 250 nm or less.
10. The semiconductor ferroelectric memory transistor according to claim 2 , wherein the first or third insulator has a film thickness of 15 nm or less.
11. The semiconductor ferroelectric memory transistor according to claim 3 , wherein the insulator has a film thickness of 250 nm or less.
12. The semiconductor ferroelectric memory transistor according to claim 3 , wherein the first or third insulator has a film thickness of 15 nm or less.
13. The semiconductor ferroelectric memory transistor according to claim 4 , wherein the insulator has a film thickness of 250 nm or less.
14. The semiconductor ferroelectric memory transistor according to claim 4 , wherein the first or third insulator has a film thickness of 15 nm or less.
15. The method according to claim 8 , wherein the heat treatment has a temperature of 760° C. to 833° C.
16. The method according to claim 8 , wherein the insulator deposition step includes depositing a ferroelectric insulator comprised of an oxide of strontium, calcium, bismuth, and tantalum via pulse laser deposition or sputtering using a plurality of oxide targets with different ratios of composition of strontium, calcium, bismuth, and tantalum.