IP Library › Granted Patent US 9,448,955
Granted Patent B2
US 9,448,955 · App. 14/408,513 · Granted Sep 20, 2016

Method for controlling interruption in data transmission process

Inventors: Xiangfeng Lu (Beijing, CN); Xuebing Yin (Beijing, CN)
Assignee: MEMBLAZE TECHNOLOGY (BEIJING) CO., LTD.
G06F13/24G06F3/061G06F3/0659G06F3/0679G06F13/28
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Quick Facts
Patent No.
US 9,448,955
App. No.
14/408,513
Granted
Sep 20, 2016
Kind
B2
Abstract

A method of controlling interrupts in the process of data transmission used for transmitting data between an information processing device and a storage device having a flash memory includes: receiving a write request sent by the information processing device using the storage device; in response to the write request, writing data to the flash memory; sending a message to the information processing device, to indicate completion of the write request, and calculating the number of times of sending messages to the information processing device within the predetermined time interval; in which, if the number is larger than the predetermined threshold, stopping the sending messages to the information processing device.

Claims (31)

1. A method of controlling interrupts in the process of data transmission, which is used for data transmission between an information processing device and a storage device, wherein the storage device includes a flash memory, the method comprising:

receiving, at the storage device, a write request sent by the information processing device;

in response to the write request, writing data into the flash memory;

sending a message to the information processing device, to indicate completion of the write request, and

calculating a number of times of sending messages to the information processing device within a predetermined interval;

wherein, if the number is larger than a predetermined threshold, caching the messages, stopping the sending the message to the information processing device, but still writing data into the flash memory.

2. The method of claim 1 , wherein if the number of times is not greater than the predetermined threshold, allowing the message to be sent to the information processing device.

3. The method of claim 1 , wherein the information processing device sets the predetermined threshold and/or the predetermined time interval.

4. The method of claim 2 , wherein the information processing device sets the predetermined threshold and/or the predetermined time interval.

5. A storage device, includes a flash memory, a control circuit and an interface unit, wherein the control circuit also includes an interrupt controller, wherein the storage device is configured to communicably connect with an information processing device; wherein

the interface unit is configured to receive a write request from the information processing device;

the control circuit is configured to write data to the flash memory based on the write request;

the interrupt controller is configured to send an interrupt to the information processing device, to indicate the completion of the write request;

the interrupt controller is configured to count the number of times of the interrupts sent to the information processing device within the predetermined time intervals; and

the interrupt controller also is configured to compare the number of times with the predetermined threshold value, and if the number is greater than the predetermined threshold, caching the interrupts and, sending interrupts to the information processing device will be suppressed;

wherein when the interrupt controller suppresses sending interrupts to the information processing device and the control circuit still writes data into the flash memory.

6. The storage device of claim 5 , wherein if the number of times of the interrupt is not greater than the predetermined threshold, the interrupt controller is allowed to send an interrupt to the information processing device.

7. The storage device of claim 5 , wherein in response to the write request received by the interface unit from the information processing device, the control circuit caches the write request.

8. A method of controlling interrupts in the process of data transmission, which is used for data transmission between an information processing device and a storage device, the storage device including a flash memory and a buffer memory, the method comprising:

receiving, at the storage device, a write request from the information processing device;

basing on the write request, writing data to the buffer memory, and incrementing a counter;

fetching the data from the buffer memory and writing the data into the flash memory, and decrementing the counter; and

if the counter is greater than or equal to a first predetermined threshold, or the number of times of sending messages, indicating completion of the write request, to the information processing device within the predetermined time interval is greater than or equal to a second predetermined threshold, then the message is cached and is not sent to the information processing device, but data is still written into the flash memory.

9. The method of claim 8 , wherein if the counter is less than the first predetermined threshold, and a number of times of sending a message to the information processing device within a predetermined time interval is less than the second predetermined threshold, sending a message indicating completion of the write request to the information processing device.

10. A storage device includes a flash memory, a buffer memory, a control circuit and an interface unit, wherein the control circuit comprises an interrupt controller, and the storage device is configured to communicably connect with an information processing device; wherein

the interface unit is configured to receive a write request sent by the information processing device;

the control circuit, based on the write request, is configured to write data to the buffer memory, and increments the counter;

the control circuit is configured to fetch the data in the buffer memory and writes the data to the flash memory, and decrements the counter;

the interrupt controller is configured to count the number of times of sending messages which indicate completion of the write request to the information processing device within a predetermined time interval; and

if the counter is greater than or equal to a first predetermined threshold, or the number of times of sending messages, indicating the completion of the write requests, to the information processing device within the predetermined time interval is greater than or equal to a second predetermined threshold, then the message is cached and is not sent to the information processing device, but the control circuit still writes data into the flash memory.

11. The storage device of claim 10 , if the counter is greater than or equal to the first predetermined threshold, or the number of times of sending messages to the information processing device within the predetermined time interval is greater than or equal to the second predetermined threshold, then the interrupt controller stops sending the message indicating the completion of the write request to the information processing device.

Assignments (3)
CHANGE OF ADDRESS Recorded Feb 7, 2022
From: BEIJING MEMBLAZE TECHNOLOGY CO., LTD.
To: BEIJING MEMBLAZE TECHNOLOGY CO., LTD.
Reel/Frame 058963/0473 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME TO BEIJING MEMBLAZE TECHNOLOGY CO., LTD. PREVIOUSLY RECORDED ON REEL 034533 FRAME 0173. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 22, 2021
From: LIU, XIANGFENG; YIN, XUEBING
To: BEIJING MEMBLAZE TECHNOLOGY CO., LTD.
Reel/Frame 057890/0302 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2014
From: LU, XIANGFENG; YIN, XUEBING
To: MEMBLAZE TECHNOLOGY (BEIJING) CO., LTD.
Reel/Frame 034533/0173 →
Priority Claims (1)
CN 2012 1 0204774 · Jun 16, 2012 · national
Continuity (1)
Related Publication 20150193360A1 · Jul 9, 2015