Using dynamic bursts to support frequency-agile memory interfaces
The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.
1. A method for operating a memory controller, comprising:
for at least one change in a host processor host-to-memory-controller interface instantaneous data rate from a first data rate R 1 to a relatively slower data rate R 2 , decreasing an average data rate of a memory interface of a memory controller substantially proportional to R 2 /R 1 without a proportional decrease in an instantaneous data rate of the memory interface by operating the memory interface in a burst mode;
wherein the burst mode comprises interspersing low-power intervals on the memory interface between at least some memory requests corresponding to temporally adjacent host requests;
and wherein the low-power intervals comprise turning off a memory clock signal supplied by the memory interface.
2. The method of claim 1 , wherein when the average data rate of the memory controller memory interface is decreased, the instantaneous data rate of the memory interface is maintained at a full rate of a bit clock used for the memory interface when the host-to-memory-controller interface is operating at first data rate R 1 .
3. The method of claim 1 , wherein the method further comprises using a Multiplying Injection Locked Oscillator (MILO) to generate a bit clock from a reference clock, wherein the MILO is configured to generate the bit clock from either a full rate reference clock signal or a subrate reference clock signal, wherein the subrate reference clock signal is a sub-harmonic of the full rate reference clock signal.
4. The method of claim 1 , wherein operating the memory interface in the burst mode comprises:
powering up the memory interface;
communicating a burst of data across the memory interface;
powering down the memory interface; and
waiting at least a set period of time before communicating a subsequent burst of data across the memory interface.
5. The method of claim 4 , wherein waiting at least the set period of time comprises waiting for a counter to reach a pre-specified value, the pre-specified value depending on R 2 /R 1 .
6. The method of claim 4 , wherein waiting at least the set period of time comprises waiting for a FIFO pointer to reach a pre-specified trip point, the pre-specified trip point depending on R 2 /R 1 .
7. The method of claim 1 , wherein operating the memory interface in the burst mode comprises front loading a first read operation, wherein front loading the first read operation comprises:
sending the first read operation to a memory device coupled to the memory interface as soon as possible when the associated command and address are received from the memory controller; and
returning data for the first read to the memory controller at an instantaneous data rate faster than R 2 .
8. The method of claim 1 , wherein operating the interface in the burst mode involves back loading a first write operation, wherein back loading the first write operation comprises:
buffering write data received on the host-to-memory-controller interface at instantaneous data rate R 2 ; and,
after sufficient data has been buffered to allow a burst transfer on the memory interface at an instantaneous data rate faster than R 2 , bursting the write data on the memory interface.
9. The method of claim 1 , wherein for a change in the host-to-memory-controller interface instantaneous data rate from rate R 2 back to rate R 1 , ceasing burst mode operation.
10. The method of claim 1 , further comprising detecting the host-to-memory-controller interface instantaneous data rate by detecting whether a reference clock signal is operating at a full rate or one of a plurality of subrates, each subrate having a corresponding burst mode with a low-power interval setting specific to that burst mode.
11. A memory controller, comprising:
a host-to-memory-controller interface capable of operation at a plurality of instantaneous data rates R 1 , R 2 , with R 1 >R 2 ;
a memory interface that, for at least one change on the host-to-memory-controller interface from data rate R 1 to data rate R 2 , decreases an average data rate of the memory interface substantially proportional to R 2 /R 1 without a proportional decrease in an instantaneous data rate of the memory interface by operating the memory interface in a burst mode;
a burst mode controller that intersperses low-power intervals on the memory interface between at least some memory requests corresponding to temporally adjacent host requests; and
a memory clock signal driver for the memory interface, the memory clock signal driver turned off during the low-power intervals.
12. The memory controller of claim 11 , wherein each burst is clocked at a fullrate of a bit clock for the interface.
13. The memory controller of claim 11 , wherein the controller-side interface further comprises using a Multiplying Injection Locked Oscillator (MILO) to generate the bit clock from the reference clock, wherein the MILO is configured to generate the fullrate bit clock from either a fullrate reference clock signal or a subrate reference clock signal, wherein the subrate reference clock signal is a sub-harmonic of the fullrate reference clock signal.
14. The memory controller of claim 11 , wherein while operating in the burst mode, the controller-side interface is configured to:
power up portions of the controller-side interface;
communicate a burst of data;
power down portions of the controller-side interface; and
wait a fixed period of time before communicating a subsequent burst of data.
15. The memory controller of claim 14 ,
wherein while powering up the portions of the controller-side interface, the controller-side interface is configured to send a power-up signal to the one or more memory-side interfaces; and
wherein while powering down the portions of the controller-side interface, the controller-side interface is configured to send a power-down signal to the one or more memory-side interfaces.
16. The memory controller of claim 14 ,
wherein the controller-side interface includes a counter; and
wherein waiting the fixed period of time involves waiting for the counter to reach a pre-specified value which depends on the subrate.
17. The memory controller of claim 14 ,
wherein the controller-side interface includes one or more First-In-First-Out buffers (FIFOs); and
wherein waiting the fixed period of time involves waiting for a FIFO pointer in the one or more FIFOs to reach a pre-specified trip point which depends on the subrate.
18. The memory controller of claim 11 ,
wherein while operating the interface in the burst mode, the controller-side interface is configured to front load a first read operation, which involves:
sending the first read to the memory as soon as the associated command and address are received from the memory controller; and
returning data for the first read as quickly as possible to the memory controller.
19. The memory controller of claim 11 , wherein while operating the interface in the burst mode, the controller-side interface is configured to back load a first write operation, which involves waiting until almost all of the write data for a burst is received from the memory controller before sending the burst to the memory.