Array substrate and fabrication method thereof
An array substrate and a fabrication method thereof are provided. The array substrate comprises a plurality of wiring regions (S-S′) disposed in a non-display region, a plurality of signal lines ( 111, 112 ) is provided in the wiring regions (S-S′), at least part of the signal lines ( 111, 112 ) within each of the wiring regions (S-S′) are respectively formed by connecting conducting wires ( 121, 123 ) located in different layers in series; and any two of the signal lines ( 111, 112 ) within a same wiring region (S-S′) have a resistance difference within a threshold range. The same signal line ( 111, 112 ) is disposed in different layers, so that the signal line ( 111, 112 ) is bent in a plane perpendicular to the array substrate, which achieves of the extension of a length of the signal line ( 111, 112 ), and thus increases the length and resistance of the signal line ( 111, 112 ), the resistance of which needs to be increased. At the same time, the width taken by the signal line ( 111, 112 ) is not increased, so that the signal line ( 111, 112 ) has a greater density in the wiring region (S-S′), which achieves the reduction in the number of drivers and the fabrication costs, and meanwhile avoids a problem that it is not conducive to realize a narrow frame due to a large area of the non-display region, resulted from a large area taken by a single signal line ( 111, 112 ).
1. A fabrication method of an array substrate, comprising: forming signal lines which are located in a non-display region, wherein the signal lines are respectively connected with a gate line or a data line, and the signal lines are respectively formed by connecting conducting wires located in different layers in series; and
the signal lines are located within wiring regions in the non-display region of the array substrate, and any two of the signal lines within a same wiring region have a resistance difference within a threshold range; and
the signal lines within the same wiring region comprise a first signal line and a second signal line, the first signal line and the second signal line are overlapped with each other in a plan view of the array substrate;
the fabrication method comprising:
synchronously forming a gate metal layer comprising the gate line in a display region, and a plurality of discontinuous first conducting wires of each of the signal lines in the non-display region;
forming a gate insulating layer and an active layer on the gate metal layer and the first conducting wires;
forming first via holes passing through the gate insulating layer and the active layer at positions corresponding to endpoints of the first conducting wires; and
simultaneously forming a source-drain metal layer comprising a source electrode, a drain electrode and the data line on the active layer, and a second conducting wire at a position corresponding to a discontinuous location between the first conducting wires, and filling a portion of the second conducting wire within the first via holes to connect the first conducting wires and the second conducting wire in series.
2. A fabrication method of an array substrate, comprising: forming signal lines which are located in a non-display region, wherein the signal lines are respectively connected with a gate line or a data line, and the signal lines are respectively formed by connecting conducting wires located in different layers in series; and
the signal lines are located within wiring regions in the non-display region of the array substrate, and any two of the signal lines within a same wiring region have a resistance difference within a threshold range; and
the signal lines within the same wiring region comprise a first signal line and a second signal line, the first signal line crosses the second signal line in a plan view of the array substrate, and the first signal line is intersected with the second signal line at a non-zero angle;
synchronously forming a gate metal layer comprising the gate line in a display region, and a plurality of discontinuous first conducting wires of each of the signal lines in the non-display region;
forming a gate insulating layer and an active layer on the gate metal layer and the first conducting wires;
forming first via holes passing through the gate insulating layer and the active layer at positions corresponding to endpoints of the first conducting wires; and
simultaneously forming a source-drain metal layer comprising a source electrode, a drain electrode and the data line on the active layer, and a second conducting wire at a position corresponding to a discontinuous location between the first conducting wires, and filling a portion of the second conducting wire within the first via holes to connect the first conducting wires and the second conducting wire in series.