Scan test system with a test interface having a clock control unit for stretching a power shift cycle
A method generates scan patterns for testing an electronic device called DUT having a scan path. A scan tester is arranged for executing a scan shift mode and a capture mode. A scan test interface has a clock control unit for stretching a shift cycle of the scan clock in dependence of a scan clock pattern. The method determines at least one power shift cycle which is expected to cause a voltage drop of a supply voltage exceeding a predetermined threshold during respective shift cycles of the scan shift mode, and generates, in addition to the scan pattern, a scan clock pattern indicative of stretching the power shift cycle. Advantageously, a relatively high scan shift frequency may be used while avoiding detrimental effects of said voltage drop by extending the respective power shift cycle, whereby test time and yield loss are reduced.
1. Method for generating at least one scan pattern for a scan tester for scan test of an electronic device having a digital function,
the device having logical elements operationally coupled for performing the digital function and also coupled via a scan path for performing a scan test according to at least one scan pattern defining a sequence of scan-in data corresponding to a starting state of the logical elements, and
the scan tester being arranged to be coupled via a test interface to the electronic device, the test interface having a scan clock, a scan-in signal and a scan-out signal, and
the scan tester being arranged for executing
a scan shift mode in which the scan-in data is shifted from the scan tester to the logical elements via the scan path and/or device data is shifted from the logical elements to the scan tester; and
a capture mode in which the device is performing the digital function for a predetermined number of operational clock cycles; and
the test interface having a clock control unit for stretching a shift cycle of the scan clock in dependence of a scan clock pattern, and
the method comprising:
generating the scan pattern in dependence of the logical elements and the digital function;
determining at least one power shift cycle which is expected to cause a voltage drop of a supply voltage exceeding a predetermined threshold during respective shift cycles of the scan shift mode; and
generating, in addition to the scan pattern, the scan clock pattern indicative of stretching the power shift cycle.
2. The method of claim 1 , wherein the scan clock pattern comprises clock stretch data indicative of the amount of stretching of the corresponding scan clock pulse.
3. The method of claim 1 , wherein the scan clock pattern comprises dummy clock data indicative of instants where the corresponding scan clock pulse is to be omitted for stretching the power shift cycle.
4. The method as claimed in claim 1 , comprising determining a power consumption in at least a part of the electronic device during respective shift cycles of the scan shift mode, and determining the at least one power shift cycle where the power consumption exceeds a predetermined threshold.
5. The method as claimed in claim 1 , comprising determining a power consumption in at least a part of the electronic device during respective shift cycles of the scan shift mode, and comprising determining the voltage drop in dependence of the power consumption so determined.
6. The method as claimed in claim 1 , comprising defining, in the scan clock pattern, an amount of stretching in dependence of said expected drop of the supply voltage.
7. The method as claimed in claim 1 , comprising determining a power consumption in multiple parts of the electronic device during respective shift cycles of the scan shift mode, said parts having respective multiple supply lines inside the electronic device, and determining the at least one shift cycle where said expected drop of the supply voltage on any of the multiple supply lines exceeds a predetermined threshold.
8. The method as claimed in claim 1 , wherein, in the electronic device, the logical elements are coupled to at least one supply power line, and the method comprises determining an impedance characteristic of the supply power line for determining said voltage drop.
9. The method as claimed in claim 1 , wherein generating the scan pattern comprises adapting the scan pattern in dependence of the at least one power shift cycle for reducing said stretching, and subsequently adapting the scan clock pattern.
10. Scan tester for scan test of an electronic device having a digital function, the device includes logical elements operationally coupled for performing the digital function and also coupled via a scan path for performing a scan test according to at least one scan pattern defining a sequence of scan-in data corresponding to a starting state of the logical elements,
Wherein the scan tester is coupled via a test interface to the electronic device, the test interface having a scan clock, a scan-in signal and a scan-out signal, and
wherein the scan tester is configured to execute:
a scan shift mode in which the scan-in data is shifted from the scan tester to the logical elements via the scan path and/or device data is shifted from the logical elements to the scan tester, and
a capture mode in which the device is performing the digital function for a predetermined number of operational clock cycles for propagating from the starting state to a resulting state, and
wherein the test interface includes a clock control unit for stretching a power shift cycle of the scan clock in dependence of a scan clock pattern,
the scan tester comprises: the scan clock pattern indicative of stretching the power shift cycle which is expected to cause a voltage drop of a supply voltage exceeding a predetermined threshold during respective shift cycles of the scan shift mode.
11. The scan tester of claim 10 , the scan tester comprising the test interface for providing the scan clock having said stretched power shift cycle.
12. The scan tester as claimed in claim 10 , wherein the scan clock pattern comprises clock stretch data indicative of the amount of stretching of the corresponding scan clock pulse.
13. The scan tester as claimed in claim 10 , wherein the scan clock pattern comprises dummy clock data indicative of instants where the corresponding scan clock pulse is to be omitted for stretching the power shift cycle.
14. The scan tester as claimed in claim 10 , wherein the scan tester is arranged for providing a clock stretch signal based on the clock stretch data, and the clock control unit is arranged for stretching the power shift cycle based on the clock stretch signal.
15. An electronic device configured to be used with a scan tester,
the device comprising: logical elements operationally coupled for performing the digital function and also coupled via a scan path for performing a scan test according to at least one scan pattern defining a sequence of scan-in data corresponding to a starting state of the logical elements,
wherein the scan tester is coupled via a test interface to the electronic device, the test interface comprising a scan clock, a scan-in signal and a scan-out signal, and
the scan tester configured to execute:
a scan shift mode in which the scan-in data is shifted from the scan tester to the logical elements via the scan path and/or device data is shifted from the logical elements to the scan tester, and
a capture mode in which the device is performing the digital function for a predetermined number of operational clock cycles, and
the device comprising a clock control unit for stretching a shift cycle of the scan clock in dependence of a scan clock pattern, and
wherein the scan pattern comprises the scan clock pattern indicative of stretching a power shift cycle which is expected to cause a voltage drop of a supply voltage exceeding a predetermined threshold during respective shift cycles of the scan shift mode.
16. The electronic device as claimed in claim 15 , wherein the clock control unit is arranged for deriving a stretching signal from a multitude of device inputs for providing the scan clock having said stretched shift cycle that follows the power shift cycle.
17. An integrated circuit comprising the electronic device according to claim 15 .