Thin film transistor and fabrication method thereof, array substrate and display

1. A thin film transistor, comprising: a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, wherein:

the active layer comprises a first active layer, a second active layer and a third active layer, the first active layer is arranged close to the gate insulating layer, the third active layer is arranged between the first active layer and the second active layer, and the second active layer is arranged close to the source electrode and the drain electrode;

a carrier mobility of the first active layer is greater than a carrier mobility of the third active layer, and the carrier mobility of the third active layer is greater than a carrier mobility of the second active layer, wherein the first active layer comprises a ZnON semiconductor active layer, the second active layer comprises a metal doped ZnON semiconductor active layer;

wherein the thin film transistor further comprises an etching barrier layer, and the etching barrier layer is disposed on a portion of the active layer that corresponds to a gap between the source electrode and the drain electrode; and

wherein a total doping concentration of the doped metal is 0.1-10%.

2. The thin film transistor according to claim 1 , wherein a thickness of the first active layer is 1.0-1.8 times of a thickness of the second active layer.

3. The thin film transistor according to claim 1 , wherein metal element for doping the second active layer further comprises at least one of Ge, In, Sn and Bi.

4. An array substrate, comprising the thin film transistor according to claim 1 , and a pixel electrode electrically connected with the drain electrode of the thin film transistor.

5. The array substrate according to claim 4 , wherein the array substrate further comprises a common electrode.

6. The thin film transistor according to claim 1 , wherein the metal doped ZnON semiconductor active layer comprises a Ga—Al co-doped ZnON semiconductor active layer.

7. A fabrication method of a thin film transistor, comprising:

forming a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode on a substrate,

wherein the forming the active layer on the substrate comprises:

forming a first active layer, a second active layer and a third active layer on the substrate, wherein the first active layer is arranged close to the gate insulating layer, the third active layer is arranged between the first active layer and the second active layer, and the second active layer is arranged close to the source electrode and the drain electrode;

wherein a carrier mobility of the first active layer is greater than a carrier mobility of the third active layer, and the carrier mobility of the third active layer is greater than a carrier mobility of the second active layer, wherein the first active layer comprises a ZnON semiconductor active layer, the second active layer comprises a metal doped ZnON semiconductor active layer; and

wherein the method further comprises forming an etching barrier layer, and the etching barrier layer is formed on the active layer and corresponds to a gap between the source electrode and the drain electrode;

wherein the forming the active layer, the etching barrier layer, the source electrode and the drain electrode on the substrate comprises:

forming a ZnON film, a metal doped ZnON film and an etching barrier film on the substrate sequentially, and forming a photoresist layer on the etching barrier film;

performing exposure, development and etching processes on the substrate where the photoresist layer has been formed by using a half-tone mask or a gray-tone mask, and then forming the ZnON semiconductor active layer, the metal doped ZnON semiconductor active layer and the etching barrier layer;

forming a metal film on the substrate where the active layer and the etching barrier layer have been formed, and forming another photoresist layer on the metal film;

performing exposure, development and etching processes on the substrate where the another photoresist layer has been formed by using a normal mask, and then forming the source electrode and the drain electrode; and

wherein a total doping concentration of the doped metal is 0.1-10%.

8. The method according to claim 7 , wherein a thickness of the first active layer is 1.0-1.8 times of a thickness of the second active layer.

9. The method according to claim 7 , wherein metal element for doping the second active layer further comprises at least one of Ge, In, Sn and Bi.

10. The method according to claim 7 , wherein the forming the metal doped ZnON film comprises: forming the metal doped ZnON film by sputtering.

11. The method according to claim 7 , wherein the metal doped ZnON semiconductor active layer comprises a Ga—Al co-doped ZnON semiconductor active layer.

12. A fabrication method of a thin film transistor, comprising: forming a gate electrode, a gate insulating layer, an active layer, an etching barrier layer, a source electrode and a drain electrode on a substrate,

wherein the forming the active layer on the substrate comprises:

forming a first active layer, a second active layer and a third active layer on the substrate, wherein the first active layer is arranged close to the gate insulating layer, the third active layer is arranged between the first active layer and the second active layer, and the second active layer is arranged close to the source electrode and the drain electrode;

wherein a carrier mobility of the first active layer is greater than a carrier mobility of the third active layer, and the carrier mobility of the third active layer is greater than a carrier mobility of the second active layer, wherein the first active layer comprises a ZnON semiconductor active layer, the second active layer comprises a metal doped ZnON semiconductor active layer;

wherein the etching barrier layer is disposed on a portion of the active layer that corresponds to a gap between the source electrode and the drain electrode; and

wherein a total doping concentration of the doped metal is 0.1-10%.

13. The method according to claim 12 , wherein a thickness of the first active layer is 1.0-1.8 times of a thickness of the second active layer.

14. The method according to claim 12 , wherein metal element for doping the second active layer further comprises at least one of Ge, In, Sn and Bi.

15. The method according to claim 12 , wherein:

the forming the active layer, the etching barrier layer, the source electrode and the drain electrode on the substrate comprises:

forming a ZnON film, a metal doped ZnON film and an etching barrier film on the substrate sequentially, and forming a photoresist layer on the etching barrier film;

performing exposure, development and etching processes on the substrate where the photoresist layer has been formed by using a half-tone mask or a gray-tone mask, and then forming the ZnON semiconductor active layer, the metal doped ZnON semiconductor active layer and the etching barrier layer;

forming a metal film on the substrate where the active layer and the etching barrier layer have been formed, and forming another photoresist layer on the metal film; and

performing exposure, development and etching processes on the substrate where the another photoresist layer has been formed by using a normal mask, and then forming the source electrode and the drain electrode.

16. The method according to claim 15 , wherein the forming the metal doped ZnON film comprises: forming the metal doped ZnON film by sputtering.

17. The method according to claim 12 , wherein the metal doped ZnON semiconductor active layer comprises a Ga—Al co-doped ZnON semiconductor active layer.