IP Library Granted Patent US 9,395,740
Granted Patent B2
US 9,395,740 · App. 14/441,246 · Granted Jul 19, 2016

Temperature coefficient factor circuit, semiconductor device, and radar device

Inventors: Cristian Pavao-Moreira (Frouzins, FR); Birama Goumballa (Larra, FR); Didier Salle (Toulouse, FR)
Assignee: Freescale Semiconductor, Inc.
G05F3/262G05F3/24G05F3/245
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Quick Facts
Patent No.
US 9,395,740
App. No.
14/441,246
Granted
Jul 19, 2016
Kind
B2
Abstract

A temperature coefficient factor circuit is provided which generates a current which varies with temperature according to a programmable temperature coefficient factor. The temperature coefficient factor circuit comprises a first current source providing a first current with a positive temperature coefficient factor, a second current source providing a second current with a negative temperature coefficient factor, a common terminal, a first programmable amplifying current mirror, a second programmable amplifying current mirror and a current output circuit. The first programmable amplifying current mirror provides in dependence of a control signal ctrl an amplified first current to the common terminal. The second programmable amplifying current mirror conducts away in dependence of the control signal ctrl an amplified second current from the common terminal. The current output circuit provides the output current based on a difference current between the amplified first current and the amplified second current.

Claims (123)

1. A temperature coefficient factor circuit comprising:

a first current source configured to provide a first current that varies with a temperature according to a positive temperature coefficient factor, wherein the positive temperature coefficient factor has a positive value;

a second current source configured to provide a second current that varies with the temperature according to a negative temperature coefficient factor, wherein the negative temperature coefficient factor has having a negative value;

a common terminal;

a first programmable amplifying current mirror, coupled to the common terminal, and configured to conduct a first amplified current to the common terminal, wherein

a first input current is amplified by the first programmable amplifying current mirror according to a first amplification factor,

the first input current is one of the first current or the second current, and

the first programmable amplifying current mirror is, configured to adapt the first amplification factor in dependence of a control signal;

a second programmable amplifying current mirror, coupled to the common terminal, and configured to conduct a second amplified current away from the common terminal, wherein

a second input current is amplified by the second programmable amplifying current mirror according to a second amplification factor,

the second input current is another one of the first current or the second current, and

the second programmable amplifying current mirror is configured to adapt the second amplification factor in dependence of the control signal;

a current output circuit, coupled to the common terminal, and configured to conduct a difference current away from the common terminal and to provide an output current that varies with a temperature according to a required temperature coefficient factor, wherein the difference current is substantially equal to the first amplified current minus the second amplified current, and the output current is based on the difference current.

2. A temperature coefficient factor circuit according to claim 1 , wherein the first programmable amplifying current mirror comprises:

a first MOS transistor of a first type; and

a plurality of parallel arranged first mirror MOS transistors of the first type, wherein

the first MOS transistor is arranged in a current conduction path of the first input current,

at least one of the plurality of first mirror MOS transistors is coupled to the first MOS transistor,

each one of first mirror MOS transistors is configured to

mirror the first input current flowing through the first MOS transistor when coupled to the first MOS transistor, and

conduct the mirrored first input current to the common terminal, and

the first amplification factor is based on the number of first mirror MOS transistors being coupled to the first MOS transistor.

3. A temperature coefficient factor circuit, according claim 2 , wherein the first programmable amplifying current mirror is configured to connect a specific number of the plurality of the first mirror MOS transistors to the first MOS transistor in dependence of the control signal.

4. A temperature coefficient factor circuit according to claim 3 , wherein the first programmable amplifying current mirror comprises:

a first controller configured to process the control signal and to couple a specific number of the first mirror MOS transistors to the first MOS transistor, wherein the first controller is further configured to

calculate a ratio

R

=

T

C

F

wanted

-

T

C

F

2

T

C

F

wanted

-

T

C

F

1

 wherein TCFwanted is the required temperature coefficient factor for the output current of the current output circuit, TCF 1 is a temperature coefficient factor of the first input current, and TCF 2 is a temperature coefficient factor of the second input current,

find integer numbers A and B which provide, when A is divided by B, approximately the ratio R, and

couple the first mirror MOS transistors to the first MOS transistor.

5. A temperature coefficient factor circuit according to claim 1 , wherein the second programmable amplifying current mirror comprises:

a second MOS transistor of a second type; and

a plurality of parallel arranged second mirror MOS transistors of the second type, wherein

the second MOS transistor arranged in a current conduction path of the second input current,

at least one of the plurality of second mirror MOS transistors is coupled to the second MOS transistor,

each one of second mirror MOS transistors is configured to

mirror the second input current flowing through the second MOS transistor when being coupled to the second MOS transistor, and

conduct the mirrored second input current away from the common terminal, and

the second amplification factor is based on the number of second mirror MOS transistors being coupled to the second MOS transistor.

6. A temperature coefficient factor circuit according claim 5 , wherein the second programmable amplifying current mirror is configured to connect a specific number of the plurality of the second mirror MOS transistors to the second MOS transistor in dependence of the control signal.

7. A temperature coefficient factor circuit according to claim 4 , wherein the second programmable amplifying current mirror comprises:

a second controller configured to process the control signal and couple a specific number of the second mirror MOS transistors to the second MOS transistor, wherein

the second controller is configured to

calculate the same ratio R as the first controller,

find the same integer numbers A and B as the first controller, and

couple a number of B second mirror MOS transistors to the second MOS transistor.

8. A temperature coefficient factor circuit according to claim 5 , wherein the current output circuit is configured to provide the output current as a divided mirror current based on the difference current according to a division factor, the division factor being dependent on the control signal, and the current output circuit comprises:

a plurality of parallel arranged output mirror MOS transistors, and

an output MOS transistor, wherein

the output MOS transistor is arranged in a current conduction path of the output current,

at least one of the plurality of output mirror MOS transistors is arranged in a current conduction path of the difference current and is coupled to the output MOS transistor,

each one of the plurality of output mirror MOS transistors is configured to conduct a portion of the difference current when being arranged in the current conduction path of the difference current and being coupled to the output MOS transistor, and

the portion of the difference current conducted by a single output mirror MOS transistor is equal to the output current conducted by the output MOS transistor.

9. A temperature coefficient factor circuit, according to claim 8 , wherein the current output circuit is configured to arrange a specific number of the plurality of the output mirror MOS transistors in the current conduction path of the difference current, and couple the specific number of the plurality of the output mirror MOS transistors to the output MOS transistor.

10. A temperature coefficient factor circuit according to claim 7 , wherein the current output circuit comprises a third controller configured to:

process the control signal,

arrange a specific number of the output mirror MOS transistors in the current conduction path of the difference current,

couple the specific number of output mirror MOS transistors to the output MOS transistor

calculate the same ratio R as the first controller,

find the same integer numbers A and B as the first controller,

calculate C=A−B, and

arrange C output mirror MOS transistors in the current conduction path of the difference current and/or couple C output mirror MOS transistors to the output MOS transistor.

11. A temperature coefficient factor circuit according to claims 1 further comprising:

a switching unit configured to control the mirroring of the first current by the first programmable amplifying current mirror and the mirroring of the second current by the second programmable amplifying current mirror, or to control the mirroring of the first current by the second programmable amplifying current mirror and to control the mirroring of the second current by the first programmable amplifying current mirror, wherein the switching unit is configured to base the controlling on the control signal.

12. A temperature coefficient factor circuit according to claim 1 , wherein the first amplification factor and/or the second amplification factor is an integer number.

13. A temperature coefficient factor circuit according to claim 1 , wherein the first current source comprises

a first, a second and a third current path coupled between a supply voltage and a ground voltage;

a first output current path for providing the first current;

a first current mirror circuit for mirroring a current of the third current path to a current of the first current path , a current of the second current path and to the first current conducted by the first output current path, wherein

the first current path comprises a series arrangement of a first resistor and a first transistor,

the first transistor is coupled with a collector of the first transistor to the first current mirror circuit, with an emitter of the first transistor to the first resistor and with a base of the first transistor to the collector of the first transistor,

the first resistor is coupled between the first transistor and a ground voltage,

the second current path comprises a second transistor coupled with a base of the second transistor to the base of the first transistor, with a collector of the second transistor to the first current mirror circuit and with an emitter of the second transistor to the ground voltage,

the third current path comprises a third transistor coupled with a base of the third transistor to the collector of the second transistor, with a collector of the third transistor to the first current mirror circuit and with an emitter of the third transistor to the ground voltage, and

the first transistor, the second transistor and the third transistor are bipolar npn transistors with matching characteristics, the second transistor and the third transistor being equal and the first transistor and the second transistor have an emitter area ratio of N:1, wherein N is a value larger than 1 and represents the emitter area of the first transistor.

14. A temperature coefficient factor circuit according to claim 13 further comprising a first series arrangement of a first stabilizing resistor and a first stabilizing capacitor, wherein the first series arrangement is coupled in between the base of the third transistor and the ground voltage.

15. A temperature coefficient factor circuit according to claims 1 , wherein the second current source comprises:

a fourth, a fifth and a sixth current path coupled between the supply voltage and the ground voltage;

a second output current path for providing the second current;

a second current mirror circuit configured to mirror a current of the sixth current path to a current of the fourth current path, a current of the fifth current path and to the second current conducted by the second output current path, wherein

the fourth current path comprises a second resistor coupled between the second current mirror circuit and the ground voltage,

the fifth current path comprises a fourth transistor coupled with a base of the fourth transistor to a terminal of the fourth current path shared by the second resistor and the second current mirror circuit, with a collector of the fourth transistor to the second current mirror circuit and with an emitter of the fourth transistor to the ground voltage,

the sixth current path comprises a fifth transistor coupled with a base of the fifth transistor to the collector of the fourth transistor, with a collector of the fifth transistor to the second current mirror circuit and with an emitter of the fifth transistor to the ground voltage,

the fourth transistor and the fifth transistor are matching bipolar npn transistors with equal characteristics.

16. A temperature coefficient factor circuit according to claim 15 , further comprising:

a second series arrangement of a second stabilizing resistor and a second stabilizing capacitor, wherein the second series arrangement is coupled in between the base of the fifth transistor and the ground voltage.

17. A semiconductor device comprising a temperature coefficient factor circuit according to claim 1 for compensating a temperature dependent operation of a part of a circuitry of the semiconductor device or for introducing a temperature dependent operation of a part of a circuitry of the semiconductor device.

18. A radar device comprising a temperature coefficient factor circuit according to claims 1 for compensating a temperature dependent operation of a part of a circuitry of the semiconductor device or for introducing a temperature dependent operation of a part of a circuitry of the semiconductor device.

Assignments (24)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 20, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 20, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0859 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 6, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 6, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2015
From: PAVAO-MOREIRA, CRISTIAN; GOUMBALLA, BIRAMA; SALLE, DIDIER
To: FREESCALE SEMICONDUCTOR INC.
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Continuity (1)
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