I/O circuitry free of test clock coupled with destination/source circuitry
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
1. An integrated circuit comprising:
(a) a test clock lead;
(b) a test mode select lead;
(c) a clock source lead;
(d) core circuitry including destination circuitry having data inputs and including source circuitry having data outputs; and
(e) input and output circuitry having a first connection with the test mode select lead and a second connection with the clock source lead, but being free of a connection with the test clock lead, the input and output circuitry having data outputs coupled with the data inputs of the destination circuitry and having data inputs coupled with the data outputs of the source circuitry.
2. The integrated circuit of claim 1 in which the destination circuitry may be any one of an address bus, a data bus, a RAM memory, a cache memory, a register file, a FIFO, a register, a processor, a peripheral circuit, or a bus coupled to circuitry external to the integrated circuit.
3. The integrated circuit of claim 1 in which the source circuitry may be any one of an address bus, a data bus, a RAM memory, a cache memory, a register file, a FIFO, a register, a processor, a peripheral circuit, or a bus coupled to circuitry external to the integrated circuit.
4. The integrated circuit of claim 1 including a test access port having a clock input coupled to the test clock lead and a test mode select input coupled to the test mode select lead.
5. The integrated circuit of claim 1 including a test access port having a clock input coupled to the test clock lead, a test mode select input coupled to the test mode select lead, a test data input coupled to a test data in lead, and a test data output coupled to a test data out lead.