IP Library Granted Patent US 9,202,845
Granted Patent B2
US 9,202,845 · App. 14/446,419 · Granted Dec 1, 2015

Memory device having a stacked variable resistance layer

Inventors: Masumi Saitoh (Yokkaichi, JP); Takayuki Ishikawa (Yokkaichi, JP); Shosuke Fujii (Kuwana, JP); Hidenori Miyagawa (Yokkaichi, JP); Chika Tanaka (Yokohama, JP); Ichiro Mizushima (Yokkaichi, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L27/2436H01L27/2481H01L45/085H01L45/12H01L45/1233H01L45/1266H01L45/148H01L45/1616H01L45/1641
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Quick Facts
Patent No.
US 9,202,845
App. No.
14/446,419
Granted
Dec 1, 2015
Kind
B2
Abstract

A memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.

Claims (36)

1. A memory device, comprising:

a first electrode;

a second electrode including a metal, the metal being more easily ionizable than a material of the first electrode; and

a variable resistance layer disposed between the first electrode and the second electrode,

the variable resistance layer including:

a first layer having a relatively high crystallization rate; and

a second layer contacting the first layer, the second layer having a relatively low crystallization rate,

the first layer and the second layer being stacked along a direction connecting the first electrode and the second electrode.

2. The device according to claim 1 , wherein the crystallization rate of the first layer is at least 10% higher than the crystallization rate of the second layer.

3. The device according to claim 1 , wherein the variable resistance layer includes silicon.

4. The device according to claim 1 , wherein the second electrode includes at least one type of metal selected from the group consisting of silver, nickel, cobalt, aluminum, and copper.

5. The device according to claim 1 , wherein the first layer is nearer to the first electrode than the second layer.

6. A memory device, comprising:

a first electrode;

a second electrode including a metal, the metal being more easily ionizable than a material of the first electrode; and

a variable resistance layer disposed between the first electrode and the second electrode,

the variable resistance layer including:

a first layer having a relatively high crystallization rate; and

a second layer contacting the first layer, the second layer having a relatively low crystallization rate,

the first layer and the second layer being stacked along a direction connecting the first electrode and the second electrode, and

a metal layer disposed between the first electrode and the variable resistance layer, the metal layer including a metal more difficult to ionize than a material of the second electrode.

7. The device according to claim 6 , wherein the metal layer includes at least one type of metal selected from the group consisting of nickel, aluminum, and palladium.

8. The device according to claim 1 , wherein an oxygen concentration, a nitrogen concentration, or a total concentration of oxygen and nitrogen in the second layer is higher than an oxygen concentration, a nitrogen concentration, or a total concentration of oxygen and nitrogen in the first layer.

9. The device according to claim 1 , further comprising an insulating layer provided between the variable resistance layer and the second electrode.

10. A memory device, comprising:

a first electrode;

a second electrode including a metal, the metal being more easily ionizable than a material of the first electrode; and

a variable resistance layer disposed between the first electrode and the second electrode,

the variable resistance layer including:

a first layer having a relatively high crystallization rate; and

a second layer contacting the first layer, the second layer having a relatively low crystallization rate,

the first layer and the second layer being stacked along a direction connecting the first electrode and the second electrode, and

a metal layer disposed between the first electrode and the variable resistance layer, the metal layer including nickel,

the first layer being nearer to the first electrode than the second layer,

the variable resistance layer including silicon,

the second electrode including silver.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2014
From: SAITOH, MASUMI; ISHIKAWA, TAKAYUKI; FUJII, SHOSUKE; MIYAGAWA, HIDENORI; TANAKA, CHIKA; MIZUSHIMA, ICHIRO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 033422/0449 →
Priority Claims (1)
JP 2013-192386 · Sep 17, 2013 · national
Continuity (1)
Related Publication 20150076439A1 · Mar 19, 2015