Semiconductor device
A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer on the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the element A being higher than 0.33 but lower than 1.0; a surface region at the surface of the second SiC epitaxial layer containing the element A at a lower concentration than in the second SiC epitaxial layer, the ratio being higher than in the second SiC epitaxial layer; n-type first and second SiC regions; a gate insulating film; a gate electrode; a first electrode; and a second electrode.
1. A semiconductor device comprising:
an n-type first SiC epitaxial layer;
a p-type second SiC epitaxial layer provided on the first SiC epitaxial layer, the p-type second SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming at least one of a first combination or a second combination, the first combination being a combination of the element A selected from a group consisting of Al (aluminum), Ga (gallium), and In (indium) and the element D being N (nitrogen), the second combination being a combination of the element A being B (boron) and the element D being P (phosphorus), a ratio of a concentration of the element D to a concentration of the element A in the at least one of the combinations being higher than 0.33 but lower than 1.0;
a surface region provided at a surface of the p-type second SiC epitaxial layer, the surface region containing the element A at a lower concentration than the concentration of the element A in the p-type second SiC epitaxial layer, a ratio of a concentration of the element D to the concentration of the element A in the at least one of the combinations being higher than the ratio in the p-type second SiC epitaxial layer;
an n-type first SiC region provided at the surface of the p-type second SiC epitaxial layer, the n-type first SiC region having a depth equal to or greater than a thickness of the p-type second SiC epitaxial layer;
an n-type second SiC region provided at the surface of the p-type second SiC epitaxial layer, the n-type second SiC region being separated from the n-type first SiC region, the n-type second SiC region having a depth smaller than the thickness of the p-type second SiC epitaxial layer;
a gate insulating film provided on the surface region;
a gate electrode provided on the gate insulating film;
a first electrode provided on the n-type second SiC region; and
a second electrode provided on the opposite side of the n-type first SiC epitaxial layer from the first electrode.
2. The device according to claim 1 , wherein the ratio of the concentration of the element D to the concentration of the element A in the at least one of the combinations in the surface region is not lower than 0.9 and not higher than 1.1.
3. The device according to claim 2 , wherein the concentration of the element A forming at least one of the combinations in the p-type second SiC epitaxial layer is not lower than 1×10 16 cm −3 and not higher than 5×10 17 cm −3 .
4. The device according to claim 3 , wherein the ratio of the concentration of the element D to the concentration of the element A in the at least one of the combinations in the p-type second SiC epitaxial layer is higher than 0.40 but lower than 0.95.
5. The device according to claim 1 , wherein the concentration of the element A forming at least one of the combinations in the p-type second SiC epitaxial layer is not lower than 1×10 16 cm −3 and not higher than 5×10 17 cm −3 .
6. The device according to claim 1 , wherein the ratio of the concentration of the element D to the concentration of the element A in the at least one of the combinations in the p-type second SiC epitaxial layer is higher than 0.40 but lower than 0.95.
7. The device according to claim 1 , wherein an acceptor level of the element A forming at least one of the combinations in the p-type second SiC epitaxial layer is 150 meV or lower.
8. The device according to claim 1 , wherein 90% or more of the element D forming at least one of the combinations in the second SiC epitaxial layer is in a lattice site location nearest to the element A.
9. The device according to claim 1 , further comprising
an n-type SiC layer provided on the opposite side of the n-type first SiC epitaxial layer from the p-type second SiC epitaxial layer,
wherein the second electrode is in contact with the n-type SiC layer.
10. The device according to claim 1 , further comprising
a p-type SiC layer provided on the opposite side of the n-type first SiC epitaxial layer from the p-type second SiC epitaxial layer,
wherein the second electrode is in contact with the SiC layer.