IP Library › Granted Patent US 9,214,425
Granted Patent B2
US 9,214,425 · App. 14/450,109 · Granted Dec 15, 2015

Low-stress vias

Inventors: Ilyas Mohammed (Santa Clara, CA); Belgacem Haba (Saratoga, CA); Cyprian Emeka Uzoh (San Jose, CA)
Assignee: Tessera, Inc.
H01L23/5226H01L21/76898H01L23/481H01L2224/10135H01L2924/07811
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Quick Facts
Patent No.
US 9,214,425
App. No.
14/450,109
Granted
Dec 15, 2015
Kind
B2
Abstract

A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

Claims (27)

1. A component, comprising:

a substrate having a front surface and a rear surface remote therefrom, the substrate consisting essentially of a material having a coefficient of thermal expansion (CTE) less than 10 ppm/° C.;

an opening extending from the rear surface towards the front surface through the material, the opening defining an inner surface between the front and rear surfaces; and

a conductive via extending within the opening, the conductive via including a metal region overlying the inner surface and having a plurality of cavities trapped therein,

wherein one or more axially facing regions of the metal region include a boundary material deposited into a subset of the cavities within the metal region, the boundary material extending to a depth below the respective front or rear surface.

2. The component as claimed in claim 1 , wherein the conductive via also includes a barrier metal layer between the metal region and the inner surface, the barrier metal layer being a metal different than the metal of the metal region.

3. The component as claimed in claim 2 , wherein the metal region is a first metal region and the barrier metal layer is a first barrier metal layer, wherein the conductive via also includes a second metal layer overlying the first barrier metal layer and a third barrier metal layer between the first metal region and the second metal layer.

4. The component as claimed in claim 1 , wherein the trapped cavities have an average diameter greater than 1 micron.

5. The component as claimed in claim 1 , further comprising a conductive contact exposed at the rear surface for interconnection with an external element, the conductive contact being electrically connected with the metal region.

6. The component as claimed in claim 1 , further comprising an insulating dielectric layer coating the inner surface defined by the opening, the dielectric layer separating and insulating the conductive via from the substrate at least within the opening.

7. The component as claimed in claim 1 , wherein the boundary material includes solder.

8. The component as claimed in claim 1 , wherein the boundary material includes a polymer medium.

9. The component as claimed in claim 1 , wherein the metal region has a dendritic metal structure.

10. A system comprising a structure according to claim 1 and one or more other electronic components electrically connected to the structure.

11. The system as claimed in claim 10 , further comprising a housing, said structure and said other electronic components being mounted to said housing.

12. A component, comprising:

a substrate having a front surface and a rear surface remote therefrom, the substrate consisting essentially of a material having a coefficient of thermal expansion (CTE) less than 10 ppm/° C.;

an opening extending from the rear surface towards the front surface through the material, the opening defining an inner surface between the front and rear surfaces; and

a conductive via extending within the opening, the conductive via including a metal region overlying the inner surface and having a plurality of cavities trapped therein,

wherein the substrate has a transition surface between the opening and at least one of the front or rear surfaces, wherein a radius of the transition surface is greater than 5% of a radius of the opening.

13. The component as claimed in claim 12 , wherein the conductive via also includes a barrier metal layer between the metal region and the inner surface, the barrier metal layer being a metal different than the metal of the metal region.

14. The component as claimed in claim 13 , wherein the metal region is a first metal region and the barrier metal layer is a first barrier metal layer, wherein the conductive via also includes a second metal layer overlying the first barrier metal layer and a third barrier metal layer between the first metal region and the second metal layer.

15. The component as claimed in claim 12 , wherein the trapped cavities have an average diameter greater than 1 micron.

16. The component as claimed in claim 12 , further comprising a conductive contact exposed at the rear surface for interconnection with an external element, the conductive contact being electrically connected with the metal region.

17. The component as claimed in claim 12 , further comprising an insulating dielectric layer coating the inner surface defined by the opening, the dielectric layer separating and insulating the conductive via from the substrate at least within the opening.

18. A system comprising a structure according to claim 12 and one or more other electronic components electrically connected to the structure.

19. The system as claimed in claim 18 , further comprising a housing, said structure and said other electronic components being mounted to said housing.

Assignments (6)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0373 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0816 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2014
From: MOHAMMED, ILYAS; HABA, BELGACEM; UZOH, CYPRIAN
To: TESSERA, INC.
Reel/Frame 034042/0737 →
Continuity (2)
Division 13193814 · Jul 29, 2011
Related Publication 20140332981A1 · Nov 13, 2014