Split-gate semiconductor device with L-shaped gate
A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.
1. A method of making a semiconductor device, comprising:
forming a dielectric layer on a substrate;
forming a gate stack having a first gate conductor and a gate dielectric structure between the first gate conductor and the dielectric layer;
forming an inter-gate dielectric structure at a sidewall of the gate stack; and
forming an L-shaped second gate conductor adjacent to the inter-gate dielectric structure and on the dielectric layer, wherein a vertical portion of the L-shaped second gate conductor is located on a side of the L-shaped second gate conductor that is opposite, relative to a center of the L-shaped second gate conductor, from a conductive structure that is higher than at least a horizontal portion of the L-shaped second gate conductor.
2. The method of claim 1 , wherein forming the L-shaped second gate conductor comprises:
forming a polycrystalline silicon (“poly”) layer over the gate stack and the inter-gate dielectric structure;
forming an oxide layer over the poly layer;
selectively etching the oxide layer to form an oxide spacer on a portion of the poly layer adjacent to the inter-gate dielectric structure; and
etching the poly layer using the oxide spacer as a mask.
3. The method of claim 2 , further comprising removing the oxide spacer.
4. The method of claim 1 , wherein forming the gate dielectric structure comprises forming two or more alternating layers of nitride and oxide dielectric films.
5. The method of claim 1 , wherein forming the dielectric layer comprises forming an oxide layer.
6. The method of claim 1 , wherein forming the inter-gate dielectric structure comprises forming two or more alternating oxide and nitride dielectric films.
7. The method of claim 1 , further comprising forming the first gate conductor as a memory gate of a split-gate memory cell.
8. The method of claim 1 , further comprising forming the L-shaped second gate conductor as a select gate of a split-gate memory cell.