Shared memory architecture for a neural simulator
Aspects of the present disclosure provide methods and apparatus for allocating memory in an artificial nervous system simulator implemented in hardware. According to certain aspects, memory resource requirements for one or more components of an artificial nervous system being simulated may be determined and portions of a shared memory pool (which may include on-chip and/or off-chip RAM) may be allocated to the components based on the determination.
1. A computer-implemented method for allocating memory in an artificial nervous system simulator implemented in hardware, comprising:
performing a simulation of a plurality of artificial neurons of an artificial nervous system;
determining memory resource requirements of each of the artificial neurons of the artificial nervous system being simulated based on at least one of a state or a type of the artificial neuron being simulated;
dynamically allocating portions of a shared memory pool to the artificial neurons based on the determination of memory resource requirements as the memory resource requirements change during the simulation, wherein the shared memory pool is implemented as a distributed architecture comprising memory banks, write clients, read clients and a router interfacing the memory banks with the write clients and the read clients; and
accessing, for each artificial neuron, the portion of the shared memory pool allocated to the artificial neuron during the simulation via the write clients and the read clients.
2. The computer-implemented method of claim 1 , wherein at least a portion of the shared memory pool comprises a memory located on a separate chip than a processor of the artificial nervous system simulator.
3. The computer-implemented method of claim 1 , wherein the allocating comprises varying an amount of the shared memory pool allocated to the artificial neurons based on the determination.
4. An apparatus for allocating memory in an artificial nervous system simulator implemented in hardware, comprising:
a plurality of processing units, each processing unit configured to perform a simulation of a different artificial neuron of an artificial nervous system;
a shared memory pool implemented as a distributed architecture comprising memory banks, write clients, read clients and a router interfacing the memory banks with the write clients and the read clients; and
a processor configured to:
determine memory resource requirements of each processing unit simulating an artificial neuron of the artificial nervous system, based on at least one of a state or a type of the artificial neuron being simulated; and
dynamically allocate portions of the shared memory pool to the processing units based on the determination of memory resource requirements as the memory resource requirements change during the simulation, wherein each of the processing units is further configured to access its allocated portion of the shared memory pool during the simulation via the write clients and the read clients.
5. The apparatus of claim 4 , wherein at least a portion of the shared memory pool comprises a memory located on a separate chip than the processor of the artificial nervous system simulator.
6. The apparatus of claim 4 , wherein the processor is also configured to vary an amount of the shared memory pool allocated to the artificial neurons based on the determination.
7. An apparatus for allocating memory in an artificial nervous system simulator implemented in hardware, comprising:
means for performing a simulation of a plurality of artificial neurons of an artificial nervous system;
means for determining memory resource requirements of each of the artificial neurons of the artificial nervous system being simulated based on at least one of a state or a type of the artificial neuron being simulated;
means for dynamically allocating portions of a shared memory pool to the artificial neurons based on the determination of memory resource requirements as the memory resource requirements change during the simulation, wherein the shared memory pool is implemented as a distributed architecture comprising memory banks, write clients, read clients and a router interfacing the memory banks with the write clients and the read clients; and
means for accessing, for each artificial neuron, the portions of the shared memory pool allocated to the artificial neuron during the simulation via the write clients and the read clients.
8. The apparatus of claim 7 , wherein at least a portion of the shared memory pool comprises a memory located on a separate chip than a processor of the artificial nervous system simulator.
9. The apparatus of claim 7 , wherein the allocating comprises varying an amount of the shared memory pool allocated to the artificial neurons based on the determination.
10. A non-transitory computer-readable medium having instructions, executable by a computer, stored thereon for allocating memory in an artificial nervous system simulator implemented in hardware, comprising:
instructions for performing a simulation of a plurality of artificial neurons of an artificial nervous system;
instructions for determining memory resource requirements of each of the artificial neurons of the artificial nervous system being simulated based on at least one of a state or a type of the artificial neuron being simulated;
instructions for dynamically allocating portions of a shared memory pool to the artificial neurons based on the determination of memory resource requirements as the memory resource requirements change during the simulation, wherein the shared memory pool is implemented as a distributed architecture comprising memory banks, write clients, read clients and a router interfacing the memory banks with the write clients and the read clients; and
instructions for accessing, for each artificial neuron, the portion of the shared memory pool allocated to the artificial neuron during the simulation via the write clients and the read clients.