Multiplication circuit providing dynamic truncation
A fixed-point multiplier providing reduced energy usage dynamically truncates received operands according to the location of computationally important bits in the operands and provides the truncated operands to a reduced width multiplier offering reduced energy usage. Information about the location of the dynamic truncation is used to properly shift the result of the multiplier to provide an approximation of full multiplication of the operands.
1. An electronic computer comprising:
a processor for execution of arithmetic and logic instructions and including a multiplication circuit for multiplication of data values, the multiplication circuit:
(i) receiving a first and second operand, the first operand having a bit length of n bits;
(ii) selecting a first subset operand from the first operand of bit length m less than n, the first subset operand selected from the first operand according to a position of a leading non-zero, non-sign bit in the first operand and truncating non-zero bits of the first operand; and
(iii) providing an output equal to a product between the subset operand and the second operand.
2. The electronic computer of claim 1 wherein the product is provided by a fixed-point multiplier limited to receiving operands no greater than m-bits in length.
3. The electronic computer of claim 2 wherein the multiplication circuit selects the first subset operand to have a most significant bit of the first subset operand equal to the leading non-zero, non-sign bit.
4. The electronic computer of claim 3 wherein the multiplication circuit includes a leading one detection circuit, an input shifter and an output shifter, the leading one detection circuit detecting a location of a most significant non-zero, non-sign bit in the first operand and wherein the leading one detection circuit controls the input shifter to select bits of the first operand for multiplication; and wherein the leading one detection circuit further controls the output shifter shifting the output to different positions in an output word provided by the leading one detection circuit.
5. The electronic computer of claim 2 wherein the multiplication circuit selects the first subset operand only from less than n/2 predetermined subsets of the first operand.
6. The electronic computer of claim 5 wherein the multiplication circuit includes a logical OR circuit, a multiplexer, and a demultiplexer, the logical OR circuit detecting a presence of a one bit in at least one of the predetermined subsets to select the first subset as a subset including a most significant non-zero, non-sign bit and wherein the logical OR circuit controls a multiplexer selecting bits of the selected predetermined subset of the first operand for multiplication; and wherein the logical OR circuit further controls the demultiplexer shifting the output to different positions in an output word provided by the multiplication circuit.
7. The electronic computer of claim 1 wherein the multiplication circuit selects the first subset operand to include a leading non-zero, non-sign bit of the first operand and only bits of lower significance than the leading non-sign bit up to the total bit length of m.
8. The electronic computer of claim 1 wherein m is greater than or equal to one-half of n.
9. The electronic computer of claim 1 wherein the multiplication circuit further receives a third operand having a bit length of n bits and selects as the second operand a subset of the third operand having a bit length m less than n selected from the third operand according to the position of a leading non-zero, non-sign bit in the third operand and truncating non-zero bits of the third operand.
10. The electronic computer of claim 9 wherein the multiplication circuit selects the second operand from the third operand to include a leading non-zero, non-sign bit of the first operand and bits of lower significance than the leading non-zero, non-sign bit.
11. The electronic computer of claim 10 wherein the multiplication circuit selects the second operand to have a most significant bit of the second operand equal to the leading non-zero, non-sign bit.
12. The electronic computer of claim 10 wherein the multiplication circuit selects the second operand only from less than n/2 predetermined subsets of the first operand.
13. The electronic computer of claim 1 wherein the electronic computer further includes a memory holding the second operand stored in memory and wherein the second operand has a bit length of n bits.
14. The electronic computer of claim 1 wherein the electronic computer includes a battery power providing power to circuitry of the electronic computer supply and at least one of a wireless communication transceiver, a graphics display screen and a camera.
15. A method of conserving electrical power in a portable electronic device having an electronic computer including a processor for execution of arithmetic and logic instructions and a multiplication circuit for multiplication of data values comprising the steps of:
(i) receiving a first and second operand, the first of operand having a bit length of n bits;
(ii) selecting a first subset operand from the first operand of bit length m less than n, the first subset operand selected from the first operand according to a position of a leading non-zero, non-sign bit in the first operand and truncating non-zero bits of the first operand; and
(iii) providing an output equal to a product between the subset operand and the second operand.
16. The method of claim 15 further including the step of receiving a third operand and selecting a second subset operand from the third operand of bit length m less than n, the second subset operand selected from the third operand according to a position of a leading non-zero, non-sign bit in the third operand and truncating non-zero bits of the third operand and using the second subset operand as the second operand.
17. The method of claim 15 further including the step of executing a program stored in non-transitory medium on the electronic computer multiplying a series of run-time varying operands with a set of predetermined operands further comprising the steps of:
(a) extracting a series of storable subsets from the predetermined operand of bit length m less than n, the storable subsets selected according to a position of a leading non-zero, non-sign bit in the predetermined operands and truncating non-zero bits of the first operand;
(b) storing the storable subsets for each predetermined operand indexed to the operand; and
(c) multiplying the first subset of the first operand by a storable subset of the second operand.