Semiconductor device with self-aligned back side features
View Patent ↗Various methods and devices that involve self-aligned features on a semiconductor on insulator process are provided. An exemplary method comprises forming a gate on a semiconductor on insulator wafer. The semiconductor on insulator wafer comprises a device region, a buried insulator, and a substrate. The exemplary method further comprises applying a treatment to the semiconductor on insulator wafer using the gate as a mask. The treatment creates a treated insulator region in the buried insulator. The exemplary method also comprises removing at least a portion of the substrate. The exemplary method also comprises, selectively removing the treated insulator region from the buried insulator to form a remaining insulator region after removing that portion of the substrate.
1. A method comprising:
forming a gate on a semiconductor on insulator wafer, wherein the semiconductor on insulator wafer comprises a device region, a buried insulator, and a substrate;
applying a treatment to the semiconductor on insulator water using the gate as a mask, wherein the treatment creates a treated insulator region in the buried insulator; removing at least a portion of the substrate; and
after removing the portion of the substrate, selectively removing the treated insulator region from the buried insulator to form a remaining insulator region aligned with the gate and exposing a back side of an active layer of the device region.
2. The method of claim 1 , further comprising:
after applying the treatment to the semiconductor on insulator wafer, bonding a handle water to the semiconductor on insulator wafer;
wherein removing at least a portion of the substrate comprises removing the entire substrate; and
wherein the handle wafer provides a stabilizing force to the device region of the semiconductor on insulator wafer while the substrate is removed and after the substrate is removed.
3. The method of claim 1 , further comprising:
after removing the treated insulator region, forming a thermally conductive layer on the remaining insulator region.
4. The method of claim 1 , wherein:
the treatment comprises the implantation of dopant ions into the buried insulator; and
the treated insulator is removed using a vapor etchant.
5. The method of claim 1 , further comprising:
after removing the treated insulator region, removing a portion of the device region;
wherein the semiconductor on insulator wafer comprises a second buried insulator and a second device region;
wherein the gate comprises a gate electrode for a channel formed in the second device region; and
wherein the device region comprises an additional gate electrode for a channel formed in the second device region.
6. The method of claim 1 , further comprising:
after removing the treated insulator region, forming a strain layer on the remaining insulator region.
7. The method of claim 4 , wherein:
the dopant ions have a lower atomic weight than carbon; and
the etchant is hydrofluoric.
8. The method of claim 5 , wherein:
the second buried insulator is thinner than the buried insulator.
9. The method of claim 6 , wherein:
removal of the treated insulator region exposes the device region; and
forming the strain layer comprises a blanket deposition of a strain material on the remaining insulator region and the device region.
10. The method of claim 9 , wherein:
the remaining insulator and the gate are both in contact with a channel formed in the device region; and
the strain layer enhances the mobility of carriers in the channel.
11. A method comprising:
forming a gate on a top side of a semiconductor on insulator wafer and above an active layer;
after forming the gate, applying a treatment to the top side of the semiconductor on insulator wafer to form a treated region in an insulator layer of the semiconductor on insulator wafer;
removing a substrate from the back side of the semiconductor on insulator wafer to expose the insulator layer; and
after removing the substrate, selectively removing the treated region from the insulator layer to expose a back side of the active layer and forming a remaining insulator region aligned with the gate;
wherein the gate is used to pattern the treated region such that the treated region is formed in a self-aligned manner.
12. The method of claim 11 , wherein:
the treatment comprises the implantation of ions into the insulator layer; and the treated region is removed using a vapor etchant.
13. The method of claim 11 , further comprising:
before removing the substrate, attaching a handle wafer to a top side of the semiconductor on insulator wafer; and
after removing the treated region, depositing a strain layer on the back side of the semiconductor on insulator wafer;
wherein the strain layer enhances the mobility of carriers in a channel located above a remaining portion of the insulator layer and below the gate.
14. The method of claim 11 , further comprising
after removing the treated insulator region, removing a portion of the device region;
wherein the semiconductor on insulator wafer comprises a second buried insulator above the buried insulator and a second device region above the device region;
wherein the gate comprises a gate electrode for a channel formed in the second device region; and
wherein the device region comprises an additional gate electrode for a channel formed in the second device region.
15. The method of claim 13 , wherein:
the semiconductor on insulator wafer comprises a silicon substrate;
the substrate is removed at least partially by grinding from the back side of the semiconductor on insulator wafer;
the insulator layer comprises silicon dioxide;
the treatment comprises the implantation of ions into the insulator layer; the treated region is removed using a vapor etchant; and
the gate controls the channel of a fully depleted transistor.
16. The method of claim 14 , wherein:
the second buried insulator is thinner than the buried insulator.