Systems and methods for mitigation of resistor nonlinearity errors in single or multiphase switching voltage regulators employing inductor DCR current sensing
Systems and methods for mitigation of resistor nonlinearity errors in a power converter are provided. In at least one embodiment, the power converter comprises at least one power switch coupled to an input voltage, a pulse width modulation (PWM) circuit for generating control pulses for the at least one power switch, at least one output inductor coupled to a respective one of the at least one power switches, a current sensor coupled in parallel with the at least one output inductor, and at least one circuit element. The current sensor comprises at least one capacitor, at least one resistor for each of the at least one output inductors, and is coupled to the PWM circuit at a current bleed node. The at least one circuit element is coupled to the current bleed node and bleeds a bleed current from the current bleed node when a power switch is turned on.
1. A method comprising:
generating control signals for at least one phase of a power converter;
monitoring the control signals to determine whether one or more of the at least one phase in the power converter is turned on; and
bleeding a bleed current from a current bleed node in the power converter when one or more of the at least one phase is turned on.
2. The method of claim 1 , wherein bleeding the bleed current comprises bleeding the current that is substantially proportional to a model resistor's resistance nonlinearity.
3. The method of claim 1 , wherein bleeding the bleed current comprises bleeding the bleed current that is dependent on a programmable scaling factor.
4. The method of claim 1 , wherein bleeding the bleed current comprises bleeding the bleed current using a resistor when one or more of the at least one phase is turned on.
5. The method of claim 1 , wherein bleeding the bleed current comprises bleeding the bleed current using at least one current controlled current source when one or more of the at least one phase is turned on.
6. The method of claim 5 , wherein generating control signals comprises generating control signals for each of at least one phases of the power converter, the power converter having a plurality of phases and wherein bleeding the bleed current from the current bleed node comprises using a plurality of current controlled current sources, each of the plurality of current controlled current sources are used for a respective one of the plurality of phases.
7. The method of claim 5 , wherein bleeding the bleed current comprises bleeding a positive current.
8. The method of claim 5 , wherein bleeding the bleed current comprises bleeding a negative current.
9. The method of claim 1 , wherein the control signals comprise pulse width modulation (PWM) signals for controlling the on-time of the at least one phase of the power converter.
10. The method of claim 9 , wherein controlling the on-time of the at least one phase of the power converter includes activating a high-side FET coupled to an input voltage using the PWM signals.
11. The method of claim 10 , wherein activating the high-side FET includes causing the input voltage to form a regulated output voltage via the at least one phase of the power converter.
12. The method of claim 1 , wherein bleeding the bleed current from the current bleed node includes coupling a bleed resistor that is coupled to the current bleed node to ground.
13. The method of claim 12 , wherein coupling the bleed resistor to ground includes activating a switch that is coupled between the bleed resistor and ground.
14. The method of claim 1 , further comprising:
sensing a phase current passing through an inductor in the power converter,
wherein bleeding the bleed current from the current bleed node in the power converter reduces error in the sensing of the phase current through the inductor.
15. The method of claim 14 , wherein sensing the phase current includes determining a voltage drop across a resistor coupled to the inductor at the current bleed node.
16. The method of claim 15 , wherein bleeding the bleed current from the current bleed node reduces a nonlinearity of the resistor due to varying voltage drops.