Forming semiconductor structure with device layers and TRL
View Patent ↗A semiconductor wafer is formed with a first device layer having active devices. A handle wafer having a trap rich layer is bonded to a top surface of the semiconductor wafer. A second device layer having a MEMS device or acoustic filter device is formed on a bottom surface of the semiconductor wafer. The second device layer is formed either by monolithic fabrication processes or layer-transfer processes.
1. An integrated circuit chip comprising:
a trap rich layer disposed over a substrate in a first wafer portion;
an inverted active device layer disposed above the trap rich layer and above a bonding layer coupling the trap rich layer to the active device layer;
a cavity formed on a back side of a semiconductor structure including the inverted active device layer; and
a micro-electromechanical systems (MEMS) device physically released by the cavity and formed in an additional active device layer on the back side of the semiconductor structure including the inverted active device layer.
2. The integrated circuit chip of claim 1 further comprising:
a plurality of conductive interconnect layers formed between the inverted active device layer and the trap rich layer.
3. The integrated circuit chip of claim 1 , wherein the inverted active device layer is formed on a silicon on insulator (SOI) wafer portion.
4. The integrated circuit chip of claim 1 , wherein the additional device layer is included within a wafer portion that is different from a wafer portion in which the inverted active device layer is disposed.
5. The integrated circuit chip of claim 1 , wherein the inverted active device layer is included within a wafer portion that is different from a wafer portion and which the trap rich layer is disposed.
6. The integrated circuit chip of claim 1 , wherein the MEMS device comprises an acoustic device.
7. The integrated circuit chip of claim 1 , wherein the MEMS device comprises an acoustic filter.
8. An integrated circuit chip comprising:
a first semiconductor wafer portion having a substrate and trap rich layer disposed over the substrate;
a second semiconductor wafer portion bonded in a face-to-face arrangement with the first semiconductor wafer portion, the second semiconductor wafer portion including a first active device layer disposed above the trap rich layer and above a bonding layer coupling the first semiconductor wafer portion to the second semiconductor wafer portion;
a cavity formed on a back side of the second semiconductor wafer portion; and
a micro-electromechanical systems (MEMS) device physically released by the cavity and formed in a second active device layer on the back side of the second semiconductor wafer portion.
9. The integrated circuit chip of claim 8 further comprising:
a plurality of conductive interconnect layers formed between the first active device layer and the trap rich layer.
10. The integrated circuit chip of claim 8 , wherein the first semiconductor wafer portion comprises a silicon on insulator (SOI) wafer portion.
11. The integrated circuit chip of claim 8 , wherein the second device layer is included within a wafer portion that is different from a wafer portion in which the inverted active device layer is disposed.
12. The integrated circuit chip of claim 8 , wherein the MEMS device comprises an acoustic device.
13. The integrated circuit chip of claim 8 , wherein the MEMS device comprises an acoustic filter.