Memory devices having select gates with P type bodies, memory strings having separate source lines and methods
View Patent ↗Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.
1. A method for programming a memory cell in a selected string of memory cells, wherein the selected string is adjacent to a non-selected string, a data line is coupled to both the selected string and the non-selected string, a first source line is coupled to the selected string, and a second source line is coupled to the non-selected string, the method comprising:
biasing the first source line to a first source voltage;
biasing the data line to a data line voltage;
biasing a drain select gate of the selected string to a drain select gate voltage; and
biasing the second source line to a second source voltage, wherein the second source voltage is higher than the first source voltage, and wherein the selected string and non-selected string are both comprised of a source-body-drain configuration that is doped p-n-p, and each of the strings includes an ohmic contact between the source lines and source regions of the strings.
2. The method of claim 1 , wherein biasing the first source line to a first source voltage comprises biasing the first source line to zero volts.
3. A method for programming a memory cell in a selected string of memory cells, wherein the selected string is adjacent to a non-selected string, a data line is coupled to both the selected string and the non-selected string, a first source line is coupled to the selected string, and a second source line is coupled to the non-selected string, the method comprising:
biasing the first source line to a first source voltage;
biasing the data line to a data line voltage;
biasing a drain select gate of the selected string to a drain select gate voltage;
biasing the second source line to a second source voltage, wherein the second source voltage is higher than the first source voltage, and wherein the selected string and non-selected string are both comprised of a source-body-drain configuration that is doped p-n-p; and
wherein the non-selected string and the selected string share a same source select gate, further comprising biasing the source select gate to zero volts.
4. The method of claim 1 , further comprising biasing a drain select gate of the non-selected string to zero volts.
5. The method of claim 1 , further including biasing a non-selected data line to a non-selected data line voltage, wherein the second source voltage is the same as the non-selected data line voltage.
6. A method for reading a memory cell in a selected string of memory cells, wherein the selected string is adjacent to a non-selected string, a data line is coupled to both the selected string and the non-selected string, a first source line is coupled to the selected string, and a second source line is coupled to the non-selected string, the method comprising:
biasing the first source line to a first source voltage;
biasing the data line to a data line voltage;
biasing a drain select gate of the selected string to a drain select gate voltage; and
biasing the second source line to a second source voltage, wherein the second source voltage is higher than the first source voltage, and wherein the selected string and non-selected string are both comprised of a source-body-drain configuration that is doped p-n-p, and each of the strings includes an ohmic contact between the source lines and source regions of the strings.
7. The method claim 6 , wherein biasing the second source line to a second source voltage comprises biasing the second source line a voltage the same as the data line voltage.
8. A method for reading a memory cell in a selected string of memory cells, wherein the selected string is adjacent to a non-selected string, a data line is coupled to both the selected string and the non-selected string, a first source line is coupled to the selected string, and a second source line is coupled to the non-selected string, the method comprising:
biasing the first source line to a first source voltage;
biasing the data line to a data line voltage;
biasing a drain select gate of the selected string to a drain select gate voltage;
biasing the second source line to a second source voltage, wherein the second source voltage is higher than the first source voltage, and wherein the selected string and non-selected string are both comprised of a source-body-drain configuration that is doped p-n-p; and
wherein the non-selected string and the selected string share a same source select gate, further comprising biasing the source select gate to five volts.
9. The method of claim 6 , further comprising biasing a drain select gate of the non-selected string to zero volts.
10. A method for programming a memory cell in a selected string of memory cells, wherein the selected string is adjacent to a non-selected string, a data line is coupled to both the selected string and the non-selected string, a first source line and a first wordline is coupled to the selected string, and a second source line and a second wordline is coupled to the non-selected string, the method comprising:
biasing the first source line to a first source voltage;
biasing the data line to a data line voltage;
biasing a drain select gate of the selected string to a drain select gate voltage;
biasing the second source line to a second source voltage at the same time as biasing the first source line to a first source voltage, wherein the second source voltage is higher than the first source voltage; and
biasing the first wordline to a third voltage, wherein the selected string and non-selected string are both comprised of a source-body-drain configuration that is doped p-n-p, and each of the strings includes an ohmic contact between the source lines and source regions of the strings.
11. The method of claim 10 , wherein biasing the first wordline to a third voltage comprises biasing the first wordline line to twenty volts.
12. The method of claim 10 , wherein biasing the second wordline to a third voltage comprises biasing the second wordline line to ten volts.
13. The method of claim 10 , wherein biasing the drain select gate of the selected string comprises biasing the drain select gate to three volts.
14. The method of claim 10 , wherein biasing the second source line to the second source voltage comprises biasing the second source line to two volts.
15. A method for reading a memory cell in a selected string of memory cells, wherein the selected string is adjacent to a non-selected string, a data line is coupled to both the selected string and the non-selected string, a first source line and a first wordline is coupled to the selected string, and a second source line and a second wordline is coupled to the non-selected string, the method comprising:
biasing the first source line to a first source voltage;
biasing the data line to a data line voltage;
biasing a drain select gate of the selected string to a drain select gate voltage;
biasing the second source line to a second source voltage at the same time as biasing the first source line to a first source voltage, wherein the second source voltage is higher than the first source voltage; and
biasing the first wordline to a third voltage, wherein the selected string and non-selected string are both comprised of a source-body-drain configuration that is doped p-n-p, and each of the strings includes an ohmic contact between the source lines and source regions of the strings.
16. The method of claim 15 , wherein biasing the first wordline to a third voltage comprises biasing the first wordline line to a reference voltage.
17. The method of claim 15 , wherein biasing the second wordline to a third voltage comprises biasing the second wordline line to five volts.
18. The method of claim 15 , wherein biasing the drain select gate of the selected string comprises biasing the drain select gate to five volts.
19. The method of claim 15 , wherein biasing the second source line to the second source voltage comprises biasing the second source line to one volt.